High-K Candidates for Use as the Gate Dielectric in Silicon Mosfets
High-K Candidates for Use as the Gate Dielectric in Silicon Mosfets
复制标题
用作硅 MOSFET 栅极电介质的高 K 候选材料
DOI：
10.1007/0-387-26089-7_2
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
K. J. Hubbard
中科院分区：
文献类型：
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作者：
D. Schlom;C. Billman;J. Haeni;J. Lettieri;P. H. Tan;Rainer Held;S. Voelk;K. J. Hubbard
国际半导体行业所面临的一个“迫在眉睫的重大挑战”是为未来基于硅的金属氧化物半导体场效应晶体管（mosfet）识别和开发一种替代栅极电介质。为了使集成电路继续遵循摩尔定律，这种替代栅极电介质需要在2007年之前完全投入生产。需要（1)具有明显高于非晶SiOi（^= 3.9）的介电常数{K），(2)与硅接触时稳定（能够承受a-900℃退火步骤）^,(3)具有足够高的带隙（4-5 eV）以提供足够低的栅漏，(4)在介电/硅界面（at）处具有低密度的电活性缺陷？(5)相当于物理厚度为4倍的sio2层（泄漏电流小得多）。< 10 k}'^'^ Si02本身不再适合，因为在这样的厚度下，由于半导体通道和栅极电极之间的电子通过Si02的量子力学隧穿，栅极漏超过1 A/cm^，并且随着Si02介电材料厚度的减小呈指数增长（约为每A的10倍）。在这里，我们报告我们的研究结果集中在
An" immediate grand challenge" identified by the international semiconductor industry is the identification and development of an alternative gate dielectric for future metal-oxide-semiconductor field-effect transistors (MOSFETs) on silicon.* This alternative gate dielectric, which needs to be fully implemented in production by 2007 in order for integrated circuits to continue to follow Moore's Law, needs (l) to have a significantly higher dielectric constant {K) than amorphous SiOi (^= 3.9),(2) to be stable in contact with silicon (capable of withstanding a-900 C annealing step)^,(3) to have a bandgap high enough (4-5 eV) to provide sufficiently low gate leakage,(4) to have a low density of electricallyactive defects at the dielectric/silicon interface (At)? and (5) to be the electrical equivalent (with a much lower leakage current) of an Si02 layer with a physical thickness, 4x? of< 10 k}'^'^ Si02 itself is no longer suitable because at such thinnesses the gate leakage, due to the quantummechanical tunneling of electrons between the semiconductor channel and gate electrode though the Si02, exceeds 1 A/cm^ and increases exponentially with decreasing thickness of the Si02 dielectric (about ten fold per A). Here we report the results of our research focused on