Test structures for delay variability
Test structures for delay variability
复制标题
延迟变化的测试结构
DOI：
10.1145/589411.589435
复制
发表时间：
2002
期刊：
影响因子：
--
通讯作者：
Frank Liu
中科院分区：
文献类型：
--
作者：
D. Boning;Joseph Panganiban;Karen Gonzalez;S. Nassif;C. McDowell;A. Gattiker;Frank Liu
随着持续的技术缩放，由于时序变化而导致的良率损失正成为一个重要的问题。具体而言，器件和互连中的随机和系统性工艺变化导致沿着不同逻辑和信号路径的可变延迟和操作速度;这些变化会侵蚀时序窗口并最终导致电路故障。本文提出了一种测试结构方法来评估工艺偏差及其对电路速度的影响，并设计了一种新的偏差测试芯片，可以相对简单地测量和评估工艺偏差和版图偏差引起的时序偏差。首先，基本的测试结构是一个九级环形振荡器（RO）; RO频率的分频读出作为电路速度的明确定义的措施。已经设计了一大系列环形振荡器测试结构，其中每个结构对特定器件或互连变化源敏感。前端线（FEOL）或器件变化敏感结构使得能够检查作为不同布局实践的函数的沟道长度变化，包括栅极长度（指状物宽度）、多个指状物之间的间隔、取向（垂直或水平）和多晶硅填充的密度。后端线（BEOL）或互连敏感结构能够检查不同金属层的电介质或金属厚度的变化以及对互连电容的影响。测试结构方法的第二个关键要素是扫描链架构，能够独立操作和读出复制的环形振荡器测试结构。在第二版测试芯片中，采用25万美元的技术设计和制造，每个芯片可以使用简单的数字控制和读出电路连接到封装芯片来测量2000多个环形振荡器。扫描链方法涉及向每个环形振荡器阅读控制字，该控制字指定振荡器是否要操作以及RO频率是否要被置于分频和输出电路的输出总线上。额外的测试芯片设计元素包括独立的环形振荡器和控制逻辑电源网格，因此也可以测量环形振荡器对电源电压的频率依赖性，从而分离沟道长度和阈值电压变化的贡献。已制造了0.25 µm版本的测试芯片，并成功地对35个芯片进行了测量和统计分析。结果表明，晶圆内的变化继续大于芯片内的变化，但是，系统的空间模式和布局依赖的变化在芯片内是实质性的，特别关注的时间（这取决于整个芯片或逻辑块的匹配信号延迟）。测试芯片可以被移植到其他先进技术，以提供关于时序变化的布局相关和空间相关工艺变化源的信息，以帮助统计时序分析以及帮助指定布局实践和设计规则以最小化变化。
With continued technology scaling, yield loss due to timing variation is becoming a significant concern. In particular, random and systematic process variation in devices and interconnect results in variable delay and operating speed along different logic and signal paths; these variations can erode timing windows and ultimately contribute to circuit failure. In this work, a test structure methodology is developed to support the evaluation of process variation and its impact on circuit speed.A newly designed variation test chip enables relatively simple measurement and evaluation of timing variation resulting from process and layout-induced variation. First, the fundamental test structure is a nine-stage ring oscillator (RO); a frequency-divided readout of the RO frequency serves as a clearly defined measure of circuit speed. A large family of ring oscillator test structures has been designed, where each structure is made sensitive to a particular device or interconnect variation source. Front-end-of-line (FEOL) or device variation sensitive structures enable examination of channel length variation as a function of different layout practices, including gate length (finger width), spacing between multiple fingers, orientation (vertical or horizontal), and density of poly fill. Back-end-of-line (BEOL) or interconnect sensitive structures enable examination of variation in dielectric or metal thickness at different metal levels and impact on interconnect capacitance.The second key element of the test structure methodology is a scan-chain architecture enabling independent operation and readout of replicated ring oscillator test structures. In this second version test chip, designed and fabricated in $0.25 m technology, over 2000 ring oscillators per chip can be measured using simple digital control and readout circuitry interfaced to the packaged chip. The scan chain approach involves reading in a control word to each ring oscillator, which specifies if that oscillator is to operate and if the RO frequency is to be put onto an output bus into frequency division and output circuitry. Additional test chip design elements include separate ring oscillator and control logic power grids, so that the frequency dependence of the ring oscillators on power supply voltage can also be measured, enabling separation of channel length and threshold voltage variation contributions.A $0.25 µm version of the test chip has been fabricated, and measurement and statistical analysis of 35 chips have been successfully conducted. Results indicate that within-wafer variation continues to be larger than within-chip variation; however, systematic spatial patterns and layout-dependent variations within the chip are substantial and of particular concern in timing (which depends on matched signal delays across a chip or logic block). The test chip can be ported to other advanced technologies to provide information on layout-dependent and spatially-dependent process variation sources of timing variation, to aid in statistical timing analysis as well as help specify layout practices and design rules to minimize variation.