Using Relocatable Bitstreams for Fault Tolerance
Using Relocatable Bitstreams for Fault Tolerance
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使用可重定位比特流实现容错
DOI：
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
B. Mullins
中科院分区：
文献类型：
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作者：
David P. Montminy;R. Baldwin;Paul D. Williams;B. Mullins
Virtex-II系列现场可编程门阵列（FPGA）的常规结构和寻址方案允许通过直接位流操作重新定位部分位流。我们的比特流翻译程序通过改变模块的部分比特流来重新定位FPGA上的模块。为了利用可重定位模块，三个容错电路设计的开发和测试。当在故障下运行时，这些设计为用重新定位的无故障模块高效且透明地更换故障模块提供支持。FPGA的架构和静态逻辑显著地限制了可重定位模块的放置，特别是当微处理器被放置在FPGA上时。
The regular structure and addressing scheme for the Virtex-IIfamily of field programmable gate arrays (FPGAs) allows the relocation of partial bitstreams through direct bitstream manipulation. Our bitstream translation program relocates modules on an FPGA by changing the partial bitstream of the module. To take advantage of relocatable modules, three fault tolerant circuit designs are developed and tested. While operating through a fault, these designs provide support for efficient and transparent replacement of the faulty module with a relocated fault-free module. The architecture of the FPGA and static logic significantly constrain the placement of relocatable modules, especially when a microprocessor is placed on the FPGA.