A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters
A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters
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DOI：
10.1109/jssc.2016.2582861
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发表时间：
2016-07
影响因子：
5.4
通讯作者：
Wei-Hsin Tseng;W. Lee;Chang-Yang Huang;Pao-Cheng Chiu
中科院分区：
文献类型：
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作者：
Wei-Hsin Tseng;W. Lee;Chang-Yang Huang;Pao-Cheng Chiu
针对蜂窝数字辅助无线发射机系统，设计了12位104 MS/S逐次逼近寄存器模数转换器(SARADC)。采用上电校准法来校正电容DAC失配，减小电容尺寸，从而降低输入缓冲器和基准发生器的电流消耗。总电容尺寸从12位匹配所需的3.6pF降至0.6pF。模数转换器模拟核心面积为0.003平方毫米。校准后，该方法在26 MHz采样率下达到88dBSFDR，在104 MHz采样率下达到76.2dBSFDR。测得的DNL和INL分别为0.5LSB和1.1LSB。该ADC通过结合数字校准、冗余、异步位循环、单调开关、25%占空比采样周期、3分贝输入增益和全动态比较器等功能，实现了高速和低功耗。1.2V/1.1V电源的单个ADC内核的功耗为0.88 mW，整个I/Q ADC的功耗为6.1 mW，包括参考发生器和输入缓冲器。该模数转换器是在28 nm的CMOS线上制作的。
A 12-bit 104 MS/s successive approximation register analog-to-digital converter (SAR ADC) is developed for a digitally-assisted wireless transmitter system for use in cellular applications. A power-on calibration method is implemented to correct capacitor DAC mismatch and reduce capacitor size, thereby lowering the current consumption of the input buffer and reference generator. The total capacitor size is reduced to 0.6 pF, from the 3.6 pF required for 12-bit matching. The ADC analog core area is 0.003 mm2. The proposed method achieves 88 dB SFDR at 26 MHz sampling rate and 76.2 dB SFDR at 104 MHz sampling rate after calibration. The measured DNL and INL are 0.5 LSB and 1.1 LSB, respectively. The ADC achieves both high speed and low power by combining several features, namely digital calibration, redundancy, asynchronous bit-cycling, monotonic switching, 25% duty-cycle sampling period, 3 dB input gain, and a fully dynamic comparator. The power consumption from 1.2 V/1.1 V supplies is 0.88 mW for a single ADC core and 6.1 mW for the entire I/Q ADC, including the reference generator and input buffers. The ADC is fabricated in 28 nm CMOS.