Architectural enhancements in Stratix-III™ and Stratix-IV™
Architectural enhancements in Stratix-III™ and Stratix-IV™
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Stratix-III™ 和 Stratix-IV™ 的架构增强
DOI：
10.1145/1508128.1508135
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
Philip Pan
中科院分区：
文献类型：
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作者：
D. Lewis;Elias Ahmed;David Cashman;Tim Vanderhoek;C. Lane;Andy Lee;Philip Pan
本文描述了Stratix-III“和Stratix-IV”FPGA结构中的结构增强。这些架构具有可编程电源管理功能，允许改变逻辑和布线的功率和性能，以最大限度地减少总功率，而不会造成任何性能损失。本文描述了用于可编程电源管理的技术，并描述了导致在这些架构中选择区域的实验评估。通过在FPGA建模工具包中添加异类存储映射，探索了该存储体系结构，并将其用于探索基于查找表的存储结构。ALM结构提供了比简单6 LUT所需更多的输入，只需简单修改即可使用，从而有效地支持基于简单双端口LUT的RAM。用LUT RAM替换Stratix-II“小内存块，并改变其他两个存储器的大小，可以减少一组基准设计的总体核心面积。
This paper describes architectural enhancements in the Stratix-III" and Stratix-IV" FPGA architectures. These architectures feature programmable power management, which allows the power and performance of logic and routing to be varied to minimize total power without any performance loss. This paper describes the technique used for programmable power management, and describes the experimental evaluation that led to the choice of regions in these architectures. The memory architecture is also explored by adding heterogeneous memory mapping to the FPGA Modeling Toolkit, and used to explore LUT based memory structures. The ALM structure provides more inputs than required for a simple 6 LUT, which can be used with simple modifications to efficiently support simple dual-ported LUT based RAM. Replacing the Stratix-II" small memory blocks with LUT RAM and changing the size of other two memories is shown to reduce overall core area across a set of benchmark designs.