3D NoC with Inductive-Coupling Links for Building-Block SiPs
3D NoC with Inductive-Coupling Links for Building-Block SiPs
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DOI：
10.1109/tc.2012.249
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发表时间：
2014-03
影响因子：
3.7
通讯作者：
Yasuhiro Take;Hiroki Matsutani;Daisuke Sasaki;M. Koibuchi;T. Kuroda;H. Amano
中科院分区：
文献类型：
--
作者：
Yasuhiro Take;Hiroki Matsutani;Daisuke Sasaki;M. Koibuchi;T. Kuroda;H. Amano
描述了一种用于构建块SIP的无线3D NoC体系结构，其中封装中的硬件组件(或芯片)的数量可以在芯片制造后改变。该架构使用电感耦合链路，无需接线即可连接两个以上的受检芯片。每个芯片都有用于上行链路和下行链路的数据收发器，以便与封装中的相邻芯片进行通信。这些芯片形成一个垂直的单向环网，以便充分利用无线方法的灵活性，使我们能够在环中添加、移除和交换芯片。为了避免环中的协议和结构死锁，我们使用了泡状流控制，它不依赖于传统的基于VC的死锁避免机制。此外，我们还提出了一种双向通信方案，利用电感耦合收发器可以动态改变通信模式，如TX、RX和Idle模式，从而形成双向环网。本文介绍了用于无线3D NoC的电感耦合收发电路，该电路可以承载高达每通道8 Gbps的高数据传输速率。它还说明了无线3D NoC的实施，该NOC具有采用65 nm工艺实施的片上路由器和收发器，以显示我们的提议的可行性。在全系统多处理器模拟器上，对单向和双向环网中的垂直泡状流控制和基于VC的传统方法与垂直广播总线在吞吐量、硬件数量和应用性能方面进行了比较。结果表明，该双向通信方案在不增加任何电感耦合收发信机的情况下，有效地提高了应用性能。此外，提出的垂直泡状流网络的性能比传统的基于VC的方法高出7.9%-12.5%，对于连接多达8个芯片的构建块SIP，路由器面积减少了33.5%。
A wireless 3D NoC architecture is described for building-block SiPs, in which the number of hardware components (or chips) in a package can be changed after chips have been fabricated. The architecture uses inductive-coupling links that can connect more than two examined dies without wire connections. Each chip has data transceivers for the uplink and downlink in order to communicate with its neighboring chips in the package. These chips form a vertical unidirectional ring network so as to fully exploit the flexibility of the wireless approach that enables us to add, remove, and swap the chips in the ring. To avoid protocol and structural deadlocks in the ring, we use bubble flow control, which does not rely on the conventional VC-based deadlock avoidance mechanism. In addition, we propose a bidirectional communication scheme to form a bidirectional ring network by using the inductive-coupling transceivers that can dynamically change the communication modes, such as TX, RX, and Idle modes. This paper illustrates the inductive-coupling transceiver circuits, which can carry high data transfer rates of up to 8 Gbps per channel, for the wireless 3D NoC. It also illustrates an implementation of a wireless 3D NoC that has on-chip routers and transceivers implemented with a 65 nm process in order to show the feasibility of our proposal. The vertical bubble flow control and conventional VC-based approach on the uni- and bidirectional ring networks are compared with the vertical broadcast bus in terms of throughput, hardware amount, and application performance using a full system multiprocessor simulator. The results show that the proposed bidirectional communication scheme efficiently improves application performance without adding any inductive-coupling transceivers. In addition, the proposed vertical bubble flow network outperforms the conventional VC-based approach by 7.9-12.5 percent with a 33.5 percent smaller router area for building-block SiPs connecting up to eight chips.