A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating
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DOI：
10.1109/tvlsi.2010.2050500
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发表时间：
2011-08
影响因子：
2.8
通讯作者：
S. Ishihara;M. Hariyama;M. Kameyama
中科院分区：
文献类型：
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作者：
S. Ishihara;M. Hariyama;M. Kameyama
提出了一种基于查找表级细粒度小开销功率门控的现场可编程门阵列。该体系结构中实现的功率门控技术可以利用异步体系结构的特点，方便地直接检测每个查找表的活动。此外，提前检测数据到达防止了唤醒延迟的增加和不必要的电源切换的功耗。由于功率门控技术具有较小的开销，功率门控域的粒度大小与单个两输入一输出查找表一样细。所提出的现场可编程门阵列采用ASPLA90 nm CMOS工艺制造，具有双阈值电压。我们使用一个名为“模板匹配”的图像处理应用程序进行评估。由于所提出的现场可编程门阵列适用于工作量动态变化的处理，因此采用了一种计算内核较小的自适应算法。在85°C下，与同步和无功率门控的异步FPGA相比，功耗分别降低了38%和15%。
This paper presents a field-programmable gate array (FPGA) based on lookup table level fine-grain power gating with small overheads. The power gating technique implemented in the proposed architecture can directly detect the activity of each look-up-table easily by exploiting features of asynchronous architectures. Moreover, detecting the data arrival in advance prevents the delay increase for waking-up and the power consumption of unnecessary power switching. Since the power gating technique has small overheads, the granularity size of a power-gated domain is as fine as a single two-input and one-output lookup table. The proposed FPGA is fabricated using the ASPLA 90-nm CMOS process with dual threshold voltages. We use an image processing application called “template matching” for evaluation. Since the proposed FPGA is suitable for processing where the workload changes dynamically, an adaptive algorithm where a small computational kernel is employed. Compared to a synchronous FPGA and an asynchronous FPGA without power gating, the power consumption is reduced respectively by 38% and 15% at 85°C.