GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM
GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM
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DOI：
10.23919/date.2019.8715270
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发表时间：
2019-03
期刊：
影响因子：
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通讯作者：
Shaahin Angizi;Jiao-Jin Sun;Wei Zhang;Deliang Fan
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文献类型：
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作者：
Shaahin Angizi;Jiao-Jin Sun;Wei Zhang;Deliang Fan
In this work, we present GraphS architecture, which transforms current Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) to massively parallel computational units capable of accelerating graph processing applications. GraphS can be leveraged to greatly reduce energy consumption dealing with underlying adjacency matrix computations, eliminating unnecessary off-chip accesses and providing ultra-high internal bandwidth. The device-to-architecture co-simulation for three social network data-sets indicate roughly 3.6× higher energy-efficiency and 5.3× speed-up over recent ReRAM crossbar. It achieves ∼4× higher energy-efficiency and 5.1× speed-up over recent processing-in-DRAM acceleration methods.
