Timing-constrained and voltage-island-aware voltage assignment
Timing-constrained and voltage-island-aware voltage assignment
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DOI：
10.1145/1146909.1147023
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发表时间：
2006-07
期刊：
影响因子：
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通讯作者：
Huaizhi Wu;Martin D. F. Wong;I-Min Liu
中科院分区：
文献类型：
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作者：
Huaizhi Wu;Martin D. F. Wong;I-Min Liu
多路复用是一种有效降低泄漏和动态功耗的方法。多电平转换器设计中的一个关键挑战是限制设计成本和对电平转换器的需求。这可以通过将不同电源电压的单元分组为少量电压岛来解决。最近，提出了一种优雅的算法来生成电压岛，该电压岛根据关键单元的放置接近度在性能要求下平衡功率与设计成本的权衡。一个先决条件是满足时序的标准电池级的初始电压分配。在本文中，我们提出了一种新的方法来产生质量的电压分配，这不仅符合时序，但也形成了良好的接近的关键细胞提供一个平滑的输入。该算法是基于有效的延迟预算和有效的计算的物理邻近Voronoi图。我们对真实的工业设计的实验表明，我们的算法导致电压岛生成的25-75%的改善，与计算时间只有线性的设计规模
Multi-Vdd is an effective method to reduce both leakage and dynamic power. A key challenge in a multi-Vdd design is to limit the design cost and the demand for level shifters. This can be tackled by grouping cells of different supply voltages into a small number of voltage islands. Recently, an elegant algorithm is proposed for generating voltage islands that balance the power versus design cost tradeoff under performance requirement, according to the placement proximity of the critical cells. One prerequisite is an initial voltage assignment at the standard cell level that meets timing. In this paper, we present a novel method to produce quality voltage assignment, which not only meets timing but also forms good proximity of the critical cells to provide with a smooth input. The algorithm is based on effective delay budgeting and efficient computation of physical proximity by Voronoi diagram. Our experiments on real industrial designs show that our algorithm leads to 25-75% improvement in the voltage island generation, with the computation time only linear to the design size