Analytic models for crosstalk delay and pulse analysis under non-ideal inputs
Analytic models for crosstalk delay and pulse analysis under non-ideal inputs
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非理想输入下串扰延迟和脉冲分析的解析模型
DOI：
10.1109/test.1997.639695
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发表时间：
1997
期刊：
影响因子：
--
通讯作者：
S. Gupta
中科院分区：
文献类型：
--
作者：
Weiyu Chen;M. Breuer;S. Gupta
在本文中，我们开发了一种通用的方法来分析串扰，以获得洞察的影响，可能会导致错误的深亚微米高速电路。我们专注于串扰由于一对线路之间的电容耦合。我们首先考虑串扰噪声表现为脉冲的情况，并表征该脉冲的最大幅度、宽度、能量和定时。封闭形式的方程量化这些脉冲属性的电路参数的值和输入过渡的上升时间的依赖关系。我们还考虑了串扰如何导致减速（加速），即增加（减少）耦合线路上的信号的上升/下降时间，当它们的输入在相反（相同）的方向上有过渡。表达式有关的减速（加速）电路参数，上升/下降时间的输入过渡，和过渡之间的偏斜。我们表明，串扰效应可以显着加剧的变化，在制造过程中。识别新的设计角点，以验证具有显著串扰效应的设计。最后，我们的分析结果提供的条件，必须满足一系列的矢量用于验证的设计，以及在存在显着的串扰的设备的制造后测试。
In this paper we develop a general methodology to analyze crosstalk to obtain insight into effects that are likely to cause errors in deep submicron high speed circuits. We focus on crosstalk due to capacitive coupling between a pair of lines. We first consider the case where crosstalk noise manifests as a pulse and characterize the maximum amplitude, width, energy and timing of this pulse. Closed form equations quantifying the dependence of these pulse attributes on the values of circuit parameters and the rise time of the input transition are derived. We also consider how crosstalk causes slowdown (speedup), i.e. increases (decreases) the rise/fall times of signals on coupled lines, when their inputs have transitions in the opposite (same) directions. Expressions relating the slowdown (speedup) to circuit parameters, the rise/fall times of the input transitions, and the skew between the transitions are derived. We show that crosstalk effects can be significantly aggravated by variations in the fabrication process. New design corners are identified for validation of designs that have significant crosstalk effects. Finally, the results of our analysis provide conditions that must be satisfied by a sequence of vectors used for validation of designs as well as post-manufacturing testing of devices in the presence of significant crosstalk.