Multi-level cell STT-RAM: Is it realistic or just a dream?
Multi-level cell STT-RAM: Is it realistic or just a dream?
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DOI：
10.1145/2429384.2429498
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发表时间：
2012-11
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影响因子：
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通讯作者：
Yaojun Zhang;Lu Zhang;Wujie Wen;Guangyu Sun;Yiran Chen
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文献类型：
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作者：
Yaojun Zhang;Lu Zhang;Wujie Wen;Guangyu Sun;Yiran Chen
自旋转移矩随机存取存储器（STT-RAM）是一种针对片上或嵌入式应用的有前途的非易失性存储器技术。近年来，为了提高STT-RAM的存储密度和可扩展性，人们进行了许多研究，如降低磁性隧道结（MTJ）器件的写入电流和开关时间。在这些努力的同时，MTJ的隧道磁阻（TMR）比的持续增加激发了多级单元（MLC）STT-RAM的发展，其允许在单个存储器单元中存储多个数据位。提出了两种MLC STT-RAM单元，即并联MLC和串联MLC。MLC STT-RAM单元的存储裕度，即，最低和最高电阻状态之间的区别被划分为多个段以用于多级数据表示。结果，MLC STT-RAM单元的性能和可靠性变得对MOS和MTJ器件变化以及MTJ切换的热致随机性更加敏感。在这项工作中，我们系统地分析了MLC STT-RAM设计的变化来源及其对读写操作的可靠性的影响。最后，从统计设计的角度，讨论了MLC MTJ的最佳器件参数，以使MLC STT-RAM单元的操作错误率最小化。我们的模拟结果表明，在目前可用的技术，串行MLC STT-RAM的读写可靠性相比，并行MLC STT-RAM表现出压倒性的优势，可以满足商业实践的要求。
Spin-transfer torque random access memory (STT-RAM) is a promising nonvolatile memory technology aiming on-chip or embedded applications. In recent years, many researches have been conducted to improve the storage density and enhance the scalability of STT-RAM, such as reducing the write current and switching time of magnetic tunneling junction (MTJ) devices. In parallel with these efforts, the continuous increasing of tunnel magneto-resistance(TMR) ratio of the MTJ inspires the development of multi-level cell (MLC) STT-RAM, which allows multiple data bits be stored in a single memory cell. Two types of MLC STT-RAM cells, namely, parallel MLC and series MLC, were also proposed. The storage margin of a MLC STT-RAM cell, i.e., the distinction between the lowest and highest resistance states, is partitioned into multiple segments for multi-level data representation. As a result, the performance and reliability of MLC STT-RAM cells become more sensitive to the MOS and MTJ device variations and the thermal-induced randomness of MTJ switching. In this work, we systematically analyze the variation sources of MLC STT-RAM designs and their impacts on the reliability of the read and write operations. On top of that, we also discuss the optimal device parameters of the MLC MTJ for the minimization of the operation error rate of the MLC STT-RAM cells from statistical design perspective. Our simulation results show that under the current available technology, series MLC STT-RAM demonstrates overwhelming benefits in the read and write reliability compared to parallel MLC STT-RAM and could potentially satisfy the requirement of commercial practices.