An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
复制标题
具有多线程同时发出指令的基本处理器体系结构
DOI：
10.1145/139669.139710
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发表时间：
1992
期刊：
影响因子：
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通讯作者：
T. Nishizawa
中科院分区：
文献类型：
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作者：
Hiroaki Hirata;K. Kimura;Satoshi Nagamine;Y. Mochizuki;A. Nishimura;Y. Nakase;T. Nishizawa
在本文中，我们提出了一个多线程的处理器架构，提高机器的吞吐量。在我们的处理器体系结构中，来自不同线程（而不是单个线程）的指令被同时发布到多个功能单元，并且这些指令可以开始执行，除非存在功能单元冲突。这种并行执行方案大大提高了功能单元的利用率。仿真结果表明，在一个九功能单元的处理器上并行执行两个和四个线程，可以分别获得比传统RISC处理器快2.02倍和3.72倍的速度。我们的架构也适用于一个循环的有效执行。为了控制循环迭代之间的功能单元冲突，我们开发了一种新的静态代码调度技术。另一个循环执行计划，通过使用多个控制流机制，我们的架构，使得它有可能并行化循环，这是很难并行化向量或VLIW机。
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a single thread) are issued simultaneously to multiple functional units, and these instructions can begin execution unless there are functional unit conflicts. This parallel execution scheme greatly improves the utilization of the functional unit. Simulation results show that by executing two and four threads in parallel on a nine-functional-unit processor, a 2.02 and a 3.72 times speed-up, respectively, can be achieved over a conventional RISC processor. Our architecture is also applicable to the efficient execution of a single loop. In order to control functional unit conflicts between loop iterations, we have developed a new static code scheduling technique. Another loop execution scheme, by using the multiple control flow mechanism of our architecture, makes it possible to parallelize loops which are difficult to parallelize in vector or VLIW machines.