Effect of Thermal Boundary Resistance of Metal/Dielectric Interface on Temperature Increase of Interconnects in Deeply Scaled VLSI.
Effect of Thermal Boundary Resistance of Metal/Dielectric Interface on Temperature Increase of Interconnects in Deeply Scaled VLSI.
复制标题
金属/电介质界面热边界电阻对深度大规模 VLSI 互连温升的影响。
DOI：
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发表时间：
2020
影响因子：
9.5
通讯作者：
Takanobu Watanabe
中科院分区：
文献类型：
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作者：
T. Zhan;K. Oda;S. Ma;M. Tomita;Zhicheng Jin;H. Takezawa;K. Mesaki;Yen‐Ju Wu;Yibin Xu;T. Matsukawa;T. Matsuki;Takanobu Watanabe
不断变窄的互连线中的温度升高加速了超大规模集成电路（VLSI）的性能和可靠性退化。在传统的热分析中，互连金属和电介质中间层之间的热边界电阻（TBR）被忽略或近似处理，导致性能和可靠性的显著不确定性。在这项研究中，我们研究了TBR之间的互连金属和介电层间层的铜，钴，钌互连在深度缩放的超大规模集成电路的温升的影响。结果表明，TBR的测量值明显高于扩散失配模型的预测值，且随衬层/阻挡层的不同，TBR的变化范围为1×10-8 ~ 1×10-7 m2 KW-1。有限元方法模拟表明，如此高的TBR可能会导致未来VLSI互连线的温度升高数百度。界面性质的表征显示了相互扩散和粘附在TBR中的重要性。对于未来的先进互连，Ru在TBR方面的散热效果优于Co。该研究为大规模集成电路的热管理提供了指导。
Temperature increase in the continuously narrowing interconnects accelerates the performance and reliability degradation of very large-scale integration (VLSI). Thermal boundary resistance (TBR) between an interconnect metal and dielectric interlayer has been neglected or treated approximately in conventional thermal analyses, resulting in significant uncertainties in performance and reliability. In this study, we investigated the effects of TBR between an interconnect metal and dielectric interlayer on temperature increase of Cu, Co, and Ru interconnects in deeply scaled VLSI. Results indicate that the measured TBR is significantly higher than the values predicted by the diffuse mismatch model and varies widely from 1×10-8 to 1×10-7 m2KW-1 depending on the liner/barrier layer used. Finite element method simulations show that such a high TBR can cause a temperature increase of hundreds of degrees in the future VLSI interconnect. Characterization of interface properties shows the significant importance of interdiffusion and adhesion in TBR. For future advanced interconnects, Ru is better than Co for heat dissipation in terms of TBR. This study provides a guideline for the thermal management in deeply scaled VLSI.