FPGA Based Electronics for PET Detector Modules With Neural Network Position Estimators

FPGA Based Electronics for PET Detector Modules With Neural Network Position Estimators
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用于具有神经网络位置估计器的 PET 探测器模块的基于 FPGA 的电子器件

DOI:
10.1109/tns.2010.2081685
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发表时间:
2011-02-01
影响因子:
1.8
通讯作者:
Bruyndonckx, Peter
Bruyndonckx, Peter
中科院分区:
工程技术3区
文献类型:
--
作者:
Wang Yonggang;Du Junwei;Bruyndonckx, Peter

文献摘要

被引文献

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我们目前正在开发一个原型单片闪烁体PET探测器模块的基础上神经网络的位置估计。检测器模块包括耦合到Hamamatsu 64通道多阳极PMT H7546B的25.5 mm x 25.5 mm x 10 LYSO晶体。用于检测器模块的电子器件读出所有信号通道,其表示伽马每个事件的散射光的分布,并且如果事件满足能量和定时选择条件,则根据预定义的神经网络算法计算撞击位置。与传统的像素化探测器相比,基于单片闪烁体的探测器模块具有设计简单、成本低、能量分辨率好等优点,但信噪比较低,信号读出方案和数据处理较为复杂。通过蒙特-卡罗模拟,比较了几种读出方案的性能。在电子学设计中采用了一种优化的读出方案,将64个通道组合成16个数字化信号。在高分辨率信号波形数字化之后,FPGA负责剩余的数字信号处理,包括神经网络定位算法的在线硬件执行。在FPGA中的优化神经网络算法的流水线实现能够处理高达每秒15.3 M的事件,而不会损失性能相比,离线实现。除了功能验证测试外,还报告了我们正在为PET系统构建的探测器模块的初步性能。
We are currently developing a prototype monolithic scintillator PET detector module based on neural network position estimators. The detector module comprises a 25.5 mm x 25.5 mm x 10 LYSO crystal coupled to a Hamamatsu 64 channels multi-anode PMT H7546B. The electronics for the detector module reads out all the signal channels, which represents the distribution of the scintillating light for gamma each event, and calculates the impinging position according to the pre-defined neural network algorithms if the event satisfies the energy and timing selection conditions. Compared with classical pixelated detectors, a monolithic scintillator based detector module features a simpler design, lower cost, and better energy resolution, but has lower signal to noise ratio and a more complicated signal readout scheme and data processing. By Monte-Carlo simulation, the performances of several readout schemes were compared. An optimized readout scheme which combines the 64 channels into 16 digitized signals was adopted in our electronics design. After the high resolution signal waveform digitization, an FPGA takes charge of the remaining digital signal processing, including the on-line hardware execution of the neural network positioning algorithms.We have implemented the electronics system for the detector modules. A pipelined implementation of the optimized neural network algorithms in the FPGA is able to process up to 15.3 M events per second without loss of performance compared to an off-line implementation. In addition to the function validation tests, the preliminary performance of the detector module we are building for a PET system is also reported.