Testable path delay fault cover for sequential circuits
Testable path delay fault cover for sequential circuits
复制标题
时序电路的可测试路径延迟故障覆盖
DOI：
10.1109/eurdac.1996.558208
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发表时间：
1996
期刊：
影响因子：
--
通讯作者：
K. Cheng
中科院分区：
文献类型：
--
作者：
Angela Krstic;S. Chakradhar;K. Cheng
我们提出了一种用于识别一组故障的算法，这些故障不必是顺序延迟测试生成器的目标。这些故障要么不能独立影响电路的性能，要么无法为其生成测试。为了发现此类故障，我们的方法利用了电路的时序行为以及时序电路中有关不可控信号的信息。它可以处理描述为两级或多级网表的时序电路。应用我们的方法的结果是减少了延迟测试生成工作并缩小了测试集。我们展示了几个 ISCAS 89 基准电路的实验结果，证明这些电路中的大量路径延迟故障不能或不必检查延迟缺陷。
We present an algorithm for identifying a set of faults that do not have to be targeted by a sequential delay test generator. These faults either cannot independently affect the performance of the circuit or no test can be generated for them. To find such faults, our methodology takes advantage of the sequential behavior of the circuit as well as of the information about uncontrollable signals in the sequential circuit. It can handle sequential circuits described as two- or multi-level netlists. The outcome of applying our methodology is reduced delay test generation effort and smaller test set. We present experimental results on several ISCAS 89 benchmark circuits demonstrating that a large number of path delay faults in these circuits either cannot or does not have to be examined for delay defects.