An event-guided approach to reducing voltage noise in processors
An event-guided approach to reducing voltage noise in processors
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DOI：
10.1109/date.2009.5090651
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发表时间：
2009-04
期刊：
影响因子：
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通讯作者：
M. Gupta;V. Reddi;G. Holloway;Gu-Yeon Wei;D. Brooks
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文献类型：
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作者：
M. Gupta;V. Reddi;G. Holloway;Gu-Yeon Wei;D. Brooks
在现代微处理器中，由电感噪声引起的供应电压波动越来越麻烦。电压ldquoemerGencyrdquo，即，超出可容忍的操作利润率的摆动会危害处理器的安全和正确操作。旨在减少功耗的技术，例如，通过时钟门控或降低名义电源电压，加剧此噪音问题，需要越来越较宽的操作利润。我们提出了一种避免电压紧急情况的事件引导，适应性的方法，该方法利用了大多数紧急情况与独特的微体系式事件相关的事实，例如cache误差或沿分支错误预测的管道冲洗。使用检查点和回滚来处理不可避免的紧急情况，我们的方法通过学习触发紧急易发的事件复发时动态适应避免机制。在收紧了电源电压利润以增加时钟频率并计算所有成本后，净结果是在15000个规格CPU2000基准的套件中，性能提高了8％。
Supply voltage fluctuations that result from inductive noise are increasingly troublesome in modern microprocessors. A voltage ldquoemergencyrdquo, i.e., a swing beyond tolerable operating margins, jeopardizes the safe and correct operation of the processor. Techniques aimed at reducing power consumption, e.g., by clock gating or by reducing nominal supply voltage, exacerbate this noise problem, requiring ever-wider operating margins. We propose an event-guided, adaptive method for avoiding voltage emergencies, which exploits the fact that most emergencies are correlated with unique microarchitectural events, such as cache misses or the pipeline flushes that follow branch mispredictions. Using checkpoint and rollback to handle unavoidable emergencies, our method adapts dynamically by learning to trigger avoidance mechanisms when emergency-prone events recur. After tightening supply voltage margins to increase clock frequency and accounting for all costs, the net result is a performance improvement of 8% across a suite of fifteen SPEC CPU2000 benchmarks.