Micro electronic systems via multifunctional additive manufacturing

Micro electronic systems via multifunctional additive manufacturing
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DOI:
10.1108/rpj-02-2017-0033
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发表时间:
2018-05
影响因子:
3.9
通讯作者:
Ji Li;T. Wasley;D. Ta;J. Shephard;J. Stringer;Patrick J. Smith;E. Esenturk;C. Connaughton;R. Harris;R. Kay
Ji Li;T. Wasley;D. Ta;J. Shephard;J. Stringer;Patrick J. Smith;E. Esenturk;C. Connaughton;R. Harris;R. Kay
中科院分区:
工程技术4区
文献类型:
--
作者:
Ji Li;T. Wasley;D. Ta;J. Shephard;J. Stringer;Patrick J. Smith;E. Esenturk;C. Connaughton;R. Harris;R. Kay

文献摘要

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目的本文旨在展示增材制造技术的改进功能,该技术通过组合多个工艺来制造封装电子产品。设计/方法/方式-这项研究的重点是通过实验与构建参数的导体沉积方法的分辨率的改善。用两种不同的低温固化各向同性导电粘合剂材料分配的材料的特征在于它们在印刷三种不同的导体设计、迹线、z轴连接和细间距倒装芯片互连中的每一种中的应用。一旦优化,演示器的尺寸可以在所选工艺和材料的限制范围内最小化。结果所提出的方法印刷z轴通过层连接是成功的支柱2毫米的高度和550微米的宽度生产。点胶特性还导致了134 µm宽和38 µm高的轨道,允许0603元件和薄收缩小外形封装集成电路的表面贴装组装。以457微米间距沉积的小型149微米倒装芯片互连也已用于封装硅裸芯片。独创性/价值-本文提出了一种改进的多功能增材制造方法,生产完全封装的多层电子系统。它讨论了新的3D打印的发展,通过层z轴连接和使用单一的导电粘合剂材料来生产所有导体。这便于在使用立体光刻将多层电路完全封装在光聚合物中之前将组件直接表面安装到这些导体上。
Purpose This paper aims to demonstrate the improved functionality of additive manufacturing technology provided by combining multiple processes for the fabrication of packaged electronics. Design/methodology/approach This research is focused on the improvement in resolution of conductor deposition methods through experimentation with build parameters. Material dispensing with two different low temperature curing isotropic conductive adhesive materials was characterised for their application in printing each of three different conductor designs, traces, z-axis connections and fine pitch flip chip interconnects. Once optimised, demonstrator size can be minimised within the limitations of the chosen processes and materials. Findings The proposed method of printing z-axis through layer connections was successful with pillars 2 mm in height and 550 µm in width produced. Dispensing characterisation also resulted in tracks 134 µm in width and 38 µm in height allowing surface mount assembly of 0603 components and thin-shrink small outline packaged integrated circuits. Small 149-µm flip chip interconnects deposited at a 457-µm pitch have also been used for packaging silicon bare die. Originality/value This paper presents an improved multifunctional additive manufacturing method to produce fully packaged multilayer electronic systems. It discusses the development of new 3D printed, through layer z-axis connections and the use of a single electrically conductive adhesive material to produce all conductors. This facilitates the surface mount assembly of components directly onto these conductors before stereolithography is used to fully package multiple layers of circuitry in a photopolymer.