Testing interconnects: a pin adjacency approach
Testing interconnects: a pin adjacency approach
复制标题
测试互连：引脚邻接方法
DOI：
10.1109/etc.1993.246596
复制
发表时间：
1993
期刊：
影响因子：
--
通讯作者：
W. Moore
中科院分区：
文献类型：
--
作者：
D. McBean;W. Moore
本文研究了一种新的用于线路板上网络间短路的故障模型，引脚邻接故障模型，以及两种算法的实现。用于检测和诊断这些桥接故障的引脚邻接检测和诊断算法。作者将网络及其缩短的可能性表示为图，并与新的算法相结合，能够生成简化的测试集。与假设任何两个网络可能短路的现有算法相比，这是一个巨大的节省，而不是新的更现实的引脚-邻接故障模型。
This paper looks at a new fault model used for shorts between nets on a PCB, the pin-adjacency fault model, and the implementation of two algorithms. The pin-adjacency detection and diagnosis algorithms for detecting and diagnosing these bridging faults. The authors represent the nets and their likelihood to short as a graph, and in conjunction with the new algorithms are able to generate reduced test sets. This represents a huge saving over existing algorithms which assume that any two nets are likely to short, as opposed to the new more realistic pin-adjacency fault model.<<ETX>>