Simulating PCI-Express Interconnect for Future System Exploration
Simulating PCI-Express Interconnect for Future System Exploration
复制标题
模拟 PCI-Express 互连以进行未来系统探索
DOI：
10.1109/iiswc.2018.8573496
复制
发表时间：
2018
期刊：
影响因子：
--
通讯作者：
N. Kim
中科院分区：
文献类型：
--
作者：
Mohammad Alian;K. Srinivasan;N. Kim
PCI - Express互连是单个计算机节点内的主要互连技术，用于将诸如网络接口卡（NIC）和GPU等片外设备连接到处理器芯片。PCI - Express的带宽和延迟常常是处理器、内存和设备交互的瓶颈，并影响所连接设备的整体性能。体系结构模拟器通常侧重于对处理器和内存的性能进行建模，而缺乏I/O设备和互连的性能模型。在这项工作中，我们在一个广为人知的体系结构模拟器中为PCI - Express互连实现了一个灵活且详细的模型。我们还实现了一个由PCI - Express设备驱动程序配置的PCI - Express设备模型。我们根据物理的第二代PCI - Express链路验证了我们的PCI - Express互连性能。我们的评估结果表明，PCI - Express模型的带宽在物理设置的19.0%以内。我们使用我们的模型评估不同的PCI - Express链路宽度和延迟，并展示其对I/O密集型应用的整体I/O性能的影响。
The PCI-Express interconnect is the dominant interconnection technology within a single computer node that is used for connecting off-chip devices such as network interface cards (NICs) and GPUs to the processor chip. The PCI-Express bandwidth and latency are often the bottleneck in the processor, memory and device interactions and impacts the overall performance of the connected devices. Architecture simulators often focus on modeling the performance of processor and memory and lack a performance model for the I/O devices and interconnections. In this work, we implement a flexible and detailed model for the PCI-Express interconnect in a widely known architecture simulator. We also implement a PCI-Express device model that is configured by a PCI-Express device driver. We validate our PCI-Express interconnect performance against a physical Gen 2 PCI-Express link. Our evaluation results show that the PCI-Express model bandwidth is within 19.0% of the physical setup. We use our model to evaluate different PCI-Express link widths and latency and show its impact on the overall I/O performance of an I/O intensive application.
影响因子：
2.3
作者：
Jung, Myoungsoo;Zhang, Jie;Kandemir, Mahmut
通讯作者：
Kandemir, Mahmut