Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors
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DOI：
10.1145/232973.233000
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发表时间：
1996-05
期刊：
影响因子：
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通讯作者：
M. Horowitz;M. Martonosi;T. Mowry;Michael D. Smith
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文献类型：
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作者：
M. Horowitz;M. Martonosi;T. Mowry;Michael D. Smith
记忆潜伏期是系统性能中的重要瓶颈，仅硬件无法充分解决。已经证明了几种有希望的软件技术可以在特定情况下成功解决此问题。但是，这些软件方法的通用性受到限制，因为当前的体系结构没有提供直接观察和对记忆行为反应的细粒度，低离子机制。为了满足这一需求，我们提出了一类新的内存操作，称为通知内存操作，该操作本质上是由有条件的分支和链接操作组合的内存操作（隐式或显式）组成的，仅当参考引用受苦时才进行缓存小姐。我们描述了为记忆操作告知内存操作的两个不同的实现---一个基于缓存结果代码，另一个基于低空陷阱的实现----发现现代的订单内和订购范围内的SuperScalar处理器已经包含大部分必要的硬件支持。我们描述了许多基于软件的内存优化如何利用告知内存操作以提高性能的信息，并以细粒度的访问控制作为案例研究来查看Cache连贯性。我们的性能结果表明，在Alpha 21164和MIPS R10000处理器上调用信息机制的运行时间开销通常足够小，可以为硬件和软件设计人员提供相当大的灵活性，并且与其他当前解决方案相比，Cache Cooherence应用程序的性能提高了性能。我们认为，将记忆操作告知未来的处理器可能会刺激更具创新性能的优化。
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to address this problem successfully in specific situations. However, the generality of these software approaches has been limited because current architectures do not provide a fine-grained, low-overhead mechanism for observing and reacting to memory behavior directly. To fill this need, we propose a new class of memory operations called informing memory operations, which essentially consist of a memory operation combined (either implicitly or explicitly) with a conditional branch-and-link operation that is taken only if the reference suffers a cache miss. We describe two different implementations of informing memory operations---one based on a cache-outcome condition code and another based on low-overhead traps---and find that modern in-order-issue and out-of-order-issue superscalar processors already contain the bulk of the necessary hardware support. We describe how a number of software-based memory optimizations can exploit informing memory operations to enhance performance, and look at cache coherence with fine-grained access control as a case study. Our performance results demonstrate that the runtime overhead of invoking the informing mechanism on the Alpha 21164 and MIPS R10000 processors is generally small enough to provide considerable flexibility to hardware and software designers, and that the cache coherence application has improved performance compared to other current solutions. We believe that the inclusion of informing memory operations in future processors may spur even more innovative performance optimizations.