Built-in-self-test of analogue circuits using optimised fault sets and transient response testing
Built-in-self-test of analogue circuits using optimised fault sets and transient response testing
复制标题
使用优化的故障集和瞬态响应测试对模拟电路进行内置自测试
DOI：
10.1109/olt.2002.1030196
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发表时间：
2002
期刊：
影响因子：
--
通讯作者：
Electrical Eng
中科院分区：
文献类型：
--
作者：
N. Axelos;J. Watson;D. Taylor;A. Platts;Dept. Electronic;Electrical Eng
瞬态响应测试已被证明是一种非常强大且经济的功能测试技术，适用于混合信号系统中的线性模拟单元。最近，通过将瞬态响应测试视为一种结构测试技术，并采用源自感应故障分析和电路灵敏度分析的优化和减少的故障集，这项工作已扩展到非线性模拟电路。这些发展非常成功，也促进了模拟电路的新颖 BIST 方法的发展。 BIST 方案对所有模拟单元采用通用片上激励，并采用专门设计的测试单元来协调短测试序列，其中包括在测试周期的关键时刻对瞬态响应进行采样并与已知参考进行比较。
Transient Response Testing has been shown to be a very powerful and economical functional test technique for linear analogue cells in mixed-signal systems. Recently this work has been extended to non-linear analogue circuits by treating Transient Response Testing as a structural test technique and employing optimised and reduced fault sets that are derived from Inductive Fault Analysis and circuit sensitivity analyses. These developments have been very successful and have also facilitated a novel BIST methodology for analogue circuits. The BIST scheme employs a generic on-chip stimulus for all analogue cells and features a specially designed test cell that coordinates a short test sequence that involves sampling the transient response at key instants in the test cycle and comparing to a known reference.