Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design
Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design
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第一个采用折纸芯片传感器设计的 Belle II SVD 梯的构建和测试
DOI：
10.1088/1748-0221/11/01/c01087
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发表时间：
2016
期刊：
影响因子：
--
通讯作者：
C. Irmler et al
中科院分区：
文献类型：
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作者：
Nobuhiro Shimizu;Nobuhiro Shimizu;C. Irmler et al
贝儿II硅顶点探测器由四层双面硅条探测器（DSSD）组成，每层由两到五个传感器组成。所有传感器都由APV25芯片单独读取，采用Origami芯片传感器概念，用于梯子的中央DSSD。芯片位于粘合在传感器顶部的柔性电路上。该概念允许低材料预算和通过每个阶梯的单个管道的切屑的有效冷却。我们提出了第一个SVD阶梯的建设和精密测量和电气测试的结果。
The Belle II Silicon Vertex Detector comprises four layers of double-sided silicon strip detectors (DSSDs), consisting of ladders with two to five sensors each. All sensors are individually read out by APV25 chips with the Origami chip-on-sensor concept for the central DSSDs of the ladders. The chips sit on flexible circuits that are glued on the top of the sensors. This concept allows a low material budget and an efficient cooling of the chips by a single pipe per ladder. We present the construction of the first SVD ladders and results from precision measurements and electrical tests.