On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines
On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines
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DOI：
10.1109/tcad.2015.2474392
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发表时间：
2016-04
影响因子：
2.9
通讯作者：
Fangming Ye;F. Firouzi;Yang Yang-Yang;K. Chakrabarty;M. Tahoori
中科院分区：
文献类型：
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作者：
Fangming Ye;F. Firouzi;Yang Yang-Yang;K. Chakrabarty;M. Tahoori
电压降是纳米级超大规模集成电路设计中的主要可靠性问题。不期望的电压下降通常是过度IR下降的结果。另一方面，当电路中的逻辑门从片上电源网络汲取高开关电流时，会发生Ldi/dt诱导的下降，并且在高时钟频率和较小的技术节点下，该问题会加剧。电压下降的后果通常是路径延迟的增加和电路操作期间间歇性故障的发生。增加保守的时序裕度（也称为保护带）是解决电压下降问题的常见做法。然而，在设计时基于最坏情况条件计算的这种静态和悲观保护带导致显著的性能损失。动态频率缩放是一种替代方法，它可以根据运行时的实际电压降动态调整时钟频率。为了使动态电压-频率有效，准确、实时地预测电压下降至关重要。我们提出了一个支持向量机（SVM）为基础的回归方法来预测电压下降，由于模式依赖的IR下降的基础上输入到芯片在运行时。此外，我们通过使用基于相关性的特征选择来减少准确预测所需的数据量。ITC'99和International Work on Logic and Synthesis'05的几个基准测试突出了所提出的方法在延迟预测精度方面的有效性。由于实时下垂预测需要硬件实现的预测器，我们提出的硬件设计和合成结果表明，支持向量机预测器的硬件开销是可以忽略不计的大型电路。
Voltage droop is a major reliability concern in nano-scale very large-scale integration designs. Undesirable voltage droop is often a result of excessive IR drop. On the other hand, Ldi/dt-induced droop occurs when logic gates in the circuit draw high-switching current from the on-chip power supply network, and this problem is exacerbated at high-clock frequencies and smaller technology nodes. A consequence of voltage droop is usually an increase in path delays and the occurrence of intermittent faults during circuit operation. The addition of conservative timing margins, also known as guardbands, is a common practice to tackle the problem of voltage droop. However, such static and pessimistic guardbands, which are calculated at design time based on worst-case conditions, lead to significant performance loss. Dynamic frequency scaling is an alternative approach that enables the dynamic adjustment of clock frequency based on the actual voltage droop seen during runtime. For dynamic voltage-frequency to be effective, accurate and real-time prediction of voltage droop is essential. We propose a support-vector machine (SVM)-based regression method to predict voltage droop due to pattern-dependent IR drop based on inputs to the chip at runtime. Moreover, we reduce the amount of data needed for accurate prediction by using correlation-based feature selection. Several benchmarks from ITC'99 and International Work on Logic and Synthesis'05 highlight the effectiveness of the proposed method in terms of delay-prediction accuracy. Since real-time droop prediction requires hardware implementation of the predictor, we present the hardware design and synthesis results to demonstrate that the hardware overhead for the SVM predictor is negligible for large circuits.