From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains
From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains
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DOI：
10.1109/access.2021.3080257
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发表时间：
2021
期刊：
影响因子：
3.9
通讯作者：
K. Z. Azar;Hadi Mardani Kamali;H. Homayoun;Avesta Sasan
中科院分区：
文献类型：
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作者：
K. Z. Azar;Hadi Mardani Kamali;H. Homayoun;Avesta Sasan
访问集成电路的扫描链的可用性是现代IC出于可测试性/调试目的的必然要求。然而，对扫描链的访问保持开放导致了IC上的许多安全威胁。它提出了具有挑战性的问题，特别是当秘密资产，如秘密信息，被放置在芯片内，如加密算法的密钥，或类似的逻辑混淆密钥。因此，为了对抗这些威胁，文献中已经提出了许多安全扫描链架构，以防止对扫描链的任何未经授权的访问。它们还保持扫描链的可用性，以实现可测试性/调试。在本文中，我们首先展示了为什么需要一个安全的扫描链架构时，安全原语，如逻辑混淆，到位。然后，我们提供了一个全面的概述，所有安全的扫描链架构开始时，密码学的地方和对手的威胁模型是非常有限的初步方法。然后，当逻辑混淆到位并且对手威胁模型更强时，引入更新和更先进的方法。因此，我们更专注于最近提出的逻辑混淆的架构。我们评估所有的安全扫描链架构的安全性和弹性，可测试性/调试时间和复杂性，面积/功耗/延迟开销。
The availability of access to Integrated Circuits’ scan chain is an inevitable requirement of modern ICs for testability/debugging purposes. However, leaving access to the scan chain OPEN resulted in numerous security threats on ICs. It raises challenging concerns particularly when the secret asset, like secret information, is placed within the chip, such as the keys of cryptographic algorithms, or similarly logic obfuscation key. So, to combat these threats, numerous secure scan chain architectures have been proposed in the literature to prevent any unauthorized access to the scan chain. They also keep the availability of the scan chain for testability/debugging. In this paper, we first show why a secure scan chain architecture is required when security primitives, like logic obfuscation, are in place. Then, we provide a holistic overview of all secure scan chain architectures starting from preliminary methods introduced when cryptography is in place and the adversary threat model is very limited. It is then followed by newer and more advanced methods introduced when logic obfuscation is in place and the adversary threat model is much stronger. Hence, we have more concentration on the architecture proposed more recently on logic obfuscation. We evaluate all secure scan chain architectures in terms of security and resiliency, testability/debugging time and complexity, and area/power/delay overhead.