Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering
Improved power side channel attack resistance of a 128-bit AES engine with random fast voltage dithering
复制标题
通过随机快速电压抖动提高 128 位 AES 引擎的电源侧通道攻击抵抗能力
DOI：
10.1109/esscirc.2017.8094523
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发表时间：
2017
期刊：
影响因子：
--
通讯作者：
S. Mukhopadhyay
中科院分区：
文献类型：
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作者：
Arvind Singh;Monodeep Kar;S. Mathew;Anand Rajan;V. De;S. Mukhopadhyay
本文演示了在130 nm CMOS中使用由集成电感电压调节器（IVR）和全数字时钟调制（ADCM）实现的随机快速电压抖动（RFVD）来提高128位AES引擎的电源侧信道攻击（PSCA）抵抗能力。在AES和IVR电源节点上测得的功率特征显示，峰值测试矢量泄漏评估（TVLA）指标降低了9倍，同时即使在500，000次加密跟踪后，也能保护加密密钥免受相关功率分析（CPA）攻击。
The paper demonstrates improved power side channel attack (PSCA) resistance of a 128-bit AES engine in 130nm CMOS using random fast voltage dithering (RFVD) enabled by integrated inductive voltage regulator (IVR) and all-digital clock modulation (ADCM). The measured power signatures at AES and IVR supply nodes show 9× reduction in peak test vector leakage assessment (TVLA) metric while also protecting encryption keys from correlation power analysis (CPA) attacks even after 500,000 encryption traces.