Design of Asynchronous Polymorphic Logic Gates for Hardware Security
Design of Asynchronous Polymorphic Logic Gates for Hardware Security
复制标题
硬件安全异步多态逻辑门设计
DOI：
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发表时间：
2021
期刊：
影响因子：
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通讯作者：
J. Di
中科院分区：
文献类型：
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作者：
Chandler Bernard;William Bryant;Richard Becker;J. Di
多态电路是在不同的工作条件下执行两种或多种不同功能的电路。本文提出了双功能异步多态逻辑门，其功能通过电源电压的变化进行选择。与之前使用进化方法生成的用于同步电路的多态门不同，这些异步多态门采用经过深思熟虑的方法设计，该方法已应用于多个工艺节点，并使用台积电 65 纳米工艺在硅中进行验证。异步多态门旨在实现“隐藏”可重构性的各个方面，而没有现场可编程门阵列（FPGA）硬件实现的典型面积和安全缺陷。
Polymorphic circuits are circuits that perform two or more different functions under varying operating conditions. This paper presents dual-function asynchronous polymorphic logic gates with functionalities selected by a change in supply voltage. Unlike previous polymorphic gates generated using an evolutionary approach for use in synchronous circuits, these asynchronous polymorphic gates are designed with a deliberate methodology that has been applied across multiple process nodes and verified in silicon using the TSMC 65nm process. The asynchronous polymorphic gates were designed to achieve aspects of "hidden" reconfigurability without the typical area and security drawbacks of field-programmable gate array (FPGA) hardware implementations.