A Field-programmable VLSI based on an asynchronous bit-serial architecture
A Field-programmable VLSI based on an asynchronous bit-serial architecture
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DOI：
10.1093/ietele/e91-c.9.1419
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发表时间：
2008-09
期刊：
影响因子：
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通讯作者：
M. Hariyama;S. Ishihara;M. Kameyama
中科院分区：
文献类型：
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作者：
M. Hariyama;S. Ishihara;M. Kameyama
为了降低功耗，提出了一种新型的异步现场可编程门阵列结构。在传统的现场可编程门阵列的动态功耗中，由于现场可编程门阵列具有复杂的开关块和大量的寄存器，因此开关块的功耗和时钟分布占主导地位。为了降低开关块的功耗和时钟分布，提出了异步位串结构。为了确保与数据路径长度无关的正确操作，我们使用了电平编码的双轨编码，并提出了其面积有效的实现。所提出的现场可编程VLSI是在90 nm的CMOS工艺中实现的。该FPVLSI的时延和功耗分别是时延敏感编码中最常用的四相双轨编码的61%和58%。
This paper presents a novel asynchronous architecture of field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay sensitive encoding.