Fully Parallel Stochastic LDPC Decoders
Fully Parallel Stochastic LDPC Decoders
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DOI：
10.1109/tsp.2008.929671
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发表时间：
2008-11
影响因子：
5.4
通讯作者：
S. Tehrani;Shie Mannor;W. Gross
中科院分区：
文献类型：
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作者：
S. Tehrani;Shie Mannor;W. Gross
随机译码是图上迭代译码的一种新方法。提出了一种全并行随机低密度奇偶校验(LDPC)译码器的硬件结构。为了获得该结构的特性，我们将该结构应用于Xilinx Virtex-4 LX200现场可编程门阵列(FPGA)器件上的非规则(1056,528)LDPC码的译码。在Eb/N0=4.25dB(误码率为10-8)的情况下，实现的解码器的时钟频率为222 MHz，吞吐量约为1.66 GB/S。在32次和16次迭代中，它的译码性能分别在浮点和积算法的0.5和0.25分贝以内，并且具有类似的误码平底行为。该解码器只使用了不到40%的查找表、触发器和可在FPGA设备上使用的IO端口。本文的结果验证了随机LDPC译码作为一种实用且具有竞争力的完全并行译码方法的潜力。
Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) decoders. To obtain the characteristics of the proposed architecture, we apply this architecture to decode an irregular state-of-the-art (1056,528) LDPC code on a Xilinx Virtex-4 LX200 field-programmable gate-array (FPGA) device. The implemented decoder achieves a clock frequency of 222 MHz and a throughput of about 1.66 Gb/s at Eb/N0=4.25 dB (a bit error rate of 10-8). It provides decoding performance within 0.5 and 0.25 dB of the floating-point sum-product algorithm with 32 and 16 iterations, respectively, and similar error-floor behavior. The decoder uses less than 40% of the lookup tables, flip-flops, and IO ports available on the FPGA device. The results provided in this paper validate the potential of stochastic LDPC decoding as a practical and competitive fully parallel decoding approach.