A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter
复制标题
具有时窗时间数字转换器的 2.1 至 2.8GHz 低相位噪声全数字频率合成器
DOI：
10.1109/jssc.2010.2076591
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发表时间：
2010
影响因子：
5.4
通讯作者：
M. Fukaishi
中科院分区：
文献类型：
--
作者：
T. Tokairin;Mitsuji Okada;Masaki Kitsunezuka;T. Maeda;M. Fukaishi
提出了一种2.1 ~ 2.8GHz低功耗全数字锁相环（ADPLL）的设计方案，该锁相环采用时间窗时间数字转换器（TDC）。时窗TDC采用两步结构，包括反相器和游标延迟时间量化器，以提高时间分辨率，从而降低相位噪声。在TDC中实现时间窗操作，其中基于单触发脉冲的操作用于低功耗。采用90 nm CMOS工艺实现的测试芯片的带内相位噪声为，环路带宽设置为500 kHz，参考信号为40 MHz，带外噪声为，失调频率为1 MHz。芯片核心占用0.37和测量的功耗是8.1 mA，从1.2 V的电源。
A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital converter (TDC) is presented. The time-windowed TDC uses a two-step structure with an inverter- and a Vernier-delay time-quantizer to improve time resolution, which results in low phase noise. Time-windowed operation is implemented in the TDC, in which a single-shot pulse-based operation is used for low power consumption. The test chip implemented in 90-nm CMOS technology exhibits in-band phase noise of , where the loop-bandwidth is set to 500 kHz with a 40-MHz reference signal, and out-band noise of at a 1-MHz offset frequency. The chip core occupies 0.37 and the measured power consumption is 8.1 mA from a 1.2-V power supply.