Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic Cores
Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic Cores
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DOI：
10.1109/tcad.2017.2706558
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发表时间：
2018-02
影响因子：
2.9
通讯作者：
Arunkumar Vijayan;S. Kiamehr;Mojtaba Ebrahimi;K. Chakrabarty;M. Tahoori
中科院分区：
文献类型：
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作者：
Arunkumar Vijayan;S. Kiamehr;Mojtaba Ebrahimi;K. Chakrabarty;M. Tahoori
辐射引起的软错误是在先进技术节点制造的电路中的主要可靠性问题。在线软错误脆弱性估计提供了利用动态容错机制的灵活性，以提高成本效益的可靠性。我们提出了一种通用的运行时方法，具有低面积和功耗开销来预测片上存储器阵列以及逻辑核心的软错误漏洞。脆弱性预测是基于信号概率（SP）的一小组触发器，选择在设计时，通过研究软错误的脆弱性和触发器的代表性工作负载的SP之间的相关性。我们利用机器学习来开发一个预测模型，可以以软件形式部署在系统中。两个处理器设计的仿真结果表明，所提出的技术可以准确地估计软错误脆弱性的片上逻辑核，如顺序流水线逻辑和功能单元，以及存储器阵列，构成的指令缓存，数据缓存，寄存器文件。
Radiation-induced soft errors are a major reliability concern in circuits fabricated at advanced technology nodes. Online soft-error vulnerability estimation offers the flexibility of exploiting dynamic fault-tolerant mechanisms for cost-effective reliability enhancement. We propose a generic run-time method with low area and power overhead to predict the soft-error vulnerability of on-chip memory arrays as well as logic cores. The vulnerability prediction is based on signal probabilities (SPs) of a small set of flip-flops, chosen at design time, by studying the correlation between the soft-error vulnerability and the flip-flop SPs for representative workloads. We exploit machine learning to develop a predictive model that can be deployed in the system in software form. Simulation results on two processor designs show that the proposed technique can accurately estimate the soft-error vulnerability of on-chip logic core, such as sequential pipeline logic and functional units as well as memory arrays that constitute the instruction cache, the data cache, and the register file.