Coss losses in silicon superjunction MOSFETs across constructions and generations

Coss losses in silicon superjunction MOSFETs across constructions and generations
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DOI:
10.1109/ispsd.2018.8393621
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发表时间:
2018-05
期刊:
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD)
影响因子:
--
通讯作者:
G. Zulauf;J. Rivas-Davila
G. Zulauf;J. Rivas-Davila
中科院分区:
其他
文献类型:
--
作者:
G. Zulauf;J. Rivas-Davila

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超级结(SJ)结构打破了硅功率MOSFET的单极材料限制,并在商业功率转换器中得到了广泛采用。在谐振应用中,这些 SJ 器件会因寄生输出电容器 Coss 的充电和放电而产生损耗,从而导致损耗随着开关频率的增加而增加。我们记录了商用 600 V 超结器件中的 COSS 损耗,表明即使采用沟槽填充外延方法生长的器件在 MHz 转换器中也具有不可忽略的损耗。此外,随着电池间距的减小和掺杂的增加,制造商内的代代进步似乎对应于更高的 COSS 损失。对于此处测试的器件,COSS 损耗在许多应用中可能超过传导损耗。
The superjunction (SJ) structure breaks the unipolar material limit of silicon power MOSFETs, and has achieved widespread adoption in commercial power converters. In resonant applications, these SJ devices experience losses due to charging and discharging the parasitic output capacitor, Coss, resulting in losses that increase with switching frequency. We document COSS losses in commercially-available 600 V superjunction devices, showing that even devices grown with the trench-filling epitaxial method have non-negligible losses in MHz converters. Further, progressing in generations within a manufacturer appears to correspond to higher COSS losses as the cell pitch is reduced and doping is increased. The COSS losses may exceed conduction losses in many applications for the devices tested here.