Profiling gem5 Simulator
Profiling gem5 Simulator
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DOI：
10.1109/ispass57527.2023.00019
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发表时间：
2023-04
期刊：
影响因子：
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通讯作者：
Johnson Umeike;Neel Patel;Alex Manley;Amin Mamandipoor;H. Yun;Mohammad Alian
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文献类型：
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作者：
Johnson Umeike;Neel Patel;Alex Manley;Amin Mamandipoor;H. Yun;Mohammad Alian
在这项工作中，我们着手寻找以下问题的答案：(1)在最先进的体系结构模拟器中瓶颈在哪里？(2)通过调整系统配置，架构模拟的运行速度可以提高多少？(3)使用硬件加速器加速软件仿真的机会是什么？我们选择gem5作为代表性的体系结构模拟器，用不同的配置运行多个模拟，在不同的服务器平台上对gem5源代码进行详细的体系结构分析，为运行模拟调整系统和体系结构设置，并讨论加速gem5成为一个重要应用程序的未来机会。我们对gem5的详细分析表明，它的性能对Ll缓存的大小非常敏感。我们的实验结果表明，与具有8KB Ll缓存的基准内核相比，具有32KB数据和指令缓存的RISC-V内核将gem5的仿真速度提高了31% ~ 61%。我们的论文是为加速基于软件的模拟器构建专用硬件和软件环境的第一步。
In this work, we set out to find the answers to the following questions: (1) Where are the bottlenecks in a state-of-theart architectural simulator? (2) How much faster can architectural simulations run by tuning system configurations? (3) What are the opportunities in accelerating software simulation using hardware accelerators? We choose gem5 as the representative architectural simulator, run several simulations with various configurations, perform a detailed architectural analysis of the gem5 source code on different server platforms, tune both system and architectural settings for running simulations, and discuss the future opportunities in accelerating gem5 as an important application. Our detailed profiling of gem5 reveals that its performance is extremely sensitive to the size of the Ll cache. Our experimental results show that a RISC-V core with 32KB data and instruction cache improves gem5’s simulation speed by 31%$\sim$61% compared with a baseline core with 8KB Ll caches. Our paper is the first step toward building specialized hardware and software environments for accelerating software-based simulators.