FPGA-based implementation of a serial RSA processor
FPGA-based implementation of a serial RSA processor
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基于 FPGA 的串行 RSA 处理器实现
DOI：
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发表时间：
2003
期刊：
影响因子：
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通讯作者：
N. Mazzocca
中科院分区：
文献类型：
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作者：
A. Mazzeo;L. Romano;G. P. Saggese;N. Mazzocca
在本文中，我们介绍了用于公钥密码学的RSA算法的硬件实现。 RSA算法包括在大整数上计算模块化指数，这些指数可以简化为重复的模块化乘法。我们提出了RSA的串行实现，该实现基于P.L.最初提出的RSA算法的优化版本。蒙哥马利（1985）。所提出的架构具有创新性，它广泛利用了Xilinx可编程设备的特定功能。与文献中的其他解决方案相比，RSA处理器的拟议实施具有较小的面积职业和可比性的性能。最终的性能水平是序列化因素的函数，我们提供了有关设计权衡的详尽讨论，就领域需求而言，对于关键长度和序列化因子的不同值。
In this paper we present an hardware implementation of the RSA algorithm for public-key cryptography. The RSA algorithm consists in the computation of modular exponentials on large integers, that can be reduced to repeated modular multiplications. We present a serial implementation of RSA, which is based upon an optimized version of the RSA algorithm originally proposed by P.L. Montgomery (1985). The proposed architecture is innovative, and it widely exploits specific capabilities of Xilinx programmable devices. As compared to other solutions in the literature, the proposed implementation of the RSA processor has smaller area occupation and comparable performance. The final performance level is a function of the serialization factor We provide a thorough discussion of design tradeoffs, in terms of area requirements vs performance, for different values of the key length and of the serialization factor.