Three Dimensional FPGA Architecture with Fewer TSVs
Three Dimensional FPGA Architecture with Fewer TSVs
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具有更少 TSV 的三维 FPGA 架构
DOI：
10.1587/transinf.2017rcp0008
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
T. Sueyoshi
中科院分区：
文献类型：
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作者：
Motoki Amagasaki;Masato Ikebe;Qian Zhao;M. Iida;T. Sueyoshi
概述三维(3D)fi可编程门阵列(ff)有望通过利用3D集成电路技术提供更高的逻辑密度以及改进的延迟和功率性能。然而，由于传统3DFGA层间连接的直通硅通孔(ff)具有较大的面积开销，因此在连接性和小尺寸之间存在固有的权衡TSV。为了在成本和性能之间取得平衡，并探索具有真实3D集成过程的3Dfi，我们提出了两种类型的3D现场可编程门阵列，并构造了用于体系结构探索的设计工具集。在以前的研究中，我们用面向下的集成方法创建了一个无TSV的3D FPGA；然而，这仅限于两层。在本文中，我们讨论了几种面朝下堆叠的现场可编程门阵列。为了最大限度地减少TSVs的数量，我们将TSVs外围放置在具有4层结构的3D-FPGA的FPGA中。根据我们的结果，当将设计限制在两层时，两层3D FPGA具有合理的性能，但当强调面积时，四层3D FPGA是更好的选择。
SUMMARY Three-dimensional (3D) field-programmable gate arrays (FPGAs) are expected to o ff er higher logic density as well as improved delay and power performance by utilizing 3D integrated circuit technology. However, because through-silicon-vias (TSVs) for conventional 3D FPGA interlayer connections have a large area overhead, there is an inherent trade-o ff between connectivity and small size. To find a balance between cost and performance, and to explore 3D FPGAs with realistic 3D integration processes, we propose two types of 3D FPGA and construct design tool sets for architecture exploration. In previous research, we created a TSV-free 3D FPGA with a face-down integration method; however, this was limited to two layers. In this paper, we discuss the face-up stacking of several face-down stacked FPGAs. To minimize the number of TSVs, we placed TSVs peripheral to the FPGAs for 3D-FPGA with 4 layers. According to our results, a 2-layer 3D FPGA has reasonable performance when limiting the design to two layers, but a 4-layer 3D FPGA is a better choice when area is emphasized.