VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization
复制标题
VPC预测:通过基于硬件的动态去虚拟化降低间接分支的成本
DOI:
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发表时间:
2007
期刊:
影响因子:
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通讯作者:
R. Cohn
中科院分区:
文献类型:
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作者:
Hyesoon Kim;José A. Joao;O. Mutlu;Chang Joo Lee;Y. Patt;R. Cohn
Indirect branches have become increasingly common in modular programs written in modern object-oriented languages and virtual machine based runtime systems. Unfortunately, the prediction accuracy of indirect branches has not improved as much as that of conditional branches. Furthermore, previously proposed indirect branch predictors usually require a significant amount of extra hardware storage and complexity, which makes them less attractive to implement.
This paper proposes a new technique for handling indirect branches, called Virtual Program Counter (VPC) prediction. The key idea of VPC prediction is to treat a single indirect branch as multiple virtual conditional branches in hardware for prediction purposes. Our technique predicts each of the virtual conditional branches using the existing conditional branch prediction hardware. Thus, no separate storage structure is required for predicting indirect branch targets.
Our evaluation shows that VPC prediction improves average performance by 26.7% compared to a commonly-used branch target buffer based predictor on 12 indirect branch intensive applications. VPC prediction achieves the performance improvement provided by at least a 12KB (and usually a 192KB) tagged target cache predictor on half of the examined applications. We show that VPC prediction can be used with any existing conditional branch prediction mechanism and that the accuracy of VPC prediction improves when a more accurate conditional branch predictor is used.