GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures
GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures
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DOI：
10.1109/tvlsi.2020.3009225
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发表时间：
2020-11-01
影响因子：
2.8
通讯作者：
Amano, Hideharu
中科院分区：
文献类型：
--
作者：
Kojima, Takuya;Nguyen Anh Vu Doan;Amano, Hideharu
由于其高能效和可编程性，粗粒度可重构架构（CGRA）预计将用于嵌入式系统，物联网（IoT）设备和边缘计算。本质上，CGRA是许多处理元件的阵列。为了充分利用这一丰富的计算资源，CGRA的编译器必须完成比通用处理器更多的任务。因此，许多研究提出了优化方法，特别是应用程序映射，因为性能和能源效率强烈依赖于编译时的优化。然而，许多工作只关注性能改进或资源最小化，尽管这样的优化目标在考虑各种用例时并不总是合适的。在这项工作中，我们提出了GenMap，一个应用程序映射框架，使用基于遗传算法的多目标优化，使用户可以根据需要设置优化标准。此外，它提供了积极的功耗优化使用我们的动态功耗模型和泄漏最小化技术。所提出的方法被施加到三个制造CGRA芯片进行评估。实验结果表明，GenMap实现了15.7%的减少线长度，同时保持处理元件的利用率相比，传统的方法。此外，根据真实的芯片实验，与其他两种方法相比，该方法的能耗降低了12.1%-46.8%，在几种架构下的加速比高达2倍。
Coarse-grained reconfigurable architectures (CGRAs) are expected to be used for embedded systems, Internet of Things (IoT) devices, and edge computing thanks to their high-energy efficiency and programmability. In essence, a CGRA is an array of numerous processing elements. To exploit this abundant computation resource, a compiler for CGRAs has to fulfill more tasks compared that for general-purpose processors. Therefore, many studies have proposed optimization methods, especially for application mapping, because the performance and energy efficiency strongly depend on optimization at compile time. However, many works focus only on performance improvement or resource minimization, although such optimization objectives are not always appropriate when considering various use cases. In this work, we propose GenMap, an application mapping framework using multiobjective optimization based on a genetic algorithm so that users can set optimization criteria as needed. Besides, it provides aggressive power optimization using our dynamic power model and leakage minimization technique. The proposed method is applied to three fabricated CGRA chips for evaluation. Experimental results show that GenMap achieves 15.7% reduction of wire length while keeping processing element utilization when compared with conventional methods. In addition, according to real chip experiments, 12.1%-46.8% of energy consumption is reduced, and up to 2x speedup is archived for several architectures when compared with other two approaches.