Variability: Modeling and Its Impact on Design
Variability: Modeling and Its Impact on Design
复制标题
可变性：建模及其对设计的影响
DOI：
10.1093/ietele/e89-c.3.342
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发表时间：
2006
期刊：
影响因子：
--
通讯作者：
H. Onodera
中科院分区：
文献类型：
--
作者：
H. Onodera
随着工艺尺度向纳米尺度的逼近，器件性能的可变性成为集成电路设计中的一个主要问题。除了不断增长的可变性之外，可变性的统计性质也随着技术的进步而发生变化。在过去，管芯到管芯的可变性，这是很好地管理的最坏情况的设计技术，占主导地位的管芯内的可变性。在现在和未来，芯片内的可变性的数量正在增加，它投下了设计方法的挑战。本文首先给出了0.35、0.18和0.13μm三种不同工艺的光变率测量结果，并对上述光变率趋势进行了解释。一个例子的模具内的变异性建模解释。芯片内的随机变化对电路性能的影响，证明了使用一个简单的数值例子。它表明，一个电路，是最佳的设计下的确定性延迟的假设是最容易受到随机波动的延迟，这清楚地表明了统计设计方法的要求。
As the technology scaling approaching nano-scale region, variability in device performance becomes a major issue in the design of integrated circuits. Besides the growing amount of variability, the statistical nature of the variability is changing as the progress of technology generation. In the past, die-to-die variability, which is well managed by the worst case design technique, dominates over within-die variability. In present and the future, the amount of within-die variability is increasing and it casts a challenge in design methodology. This paper first shows measured results of variability in three different processes of 0.35, 0.18, and 0.13μm technologies, and explains the above mentioned trend of variability. An example of modeling for the within-die variability is explained. The impact of within-die random variability on circuit performance is demonstrated using a simple numerical example. It shows that a circuit that is designed optimally under the assumption of deterministic delay is now most susceptible to random fluctuation in delay, which clearly indicates the requirement of statistical design methodology.