Fast context switching by hierarchical task allocation and reconfigurable cache
Fast context switching by hierarchical task allocation and reconfigurable cache
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通过分层任务分配和可重新配置缓存实现快速上下文切换
DOI：
10.1109/iwia.2003.1262779
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发表时间：
2003
期刊：
影响因子：
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通讯作者：
K. Tanaka
中科院分区：
文献类型：
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作者：
K. Tanaka
多线程处理器体系结构支持快速上下文切换，以容忍内存访问延迟和弥合同步间隙，从而支持有效利用执行管道。然而，它不能防止所有的管道失速；当所有处理器内置线程都处于等待状态，或者任务中没有足够的线程来填充所有可用的上下文槽时，仍然会发生停顿，因为切换活动线程的机制仅对处理器内置上下文有效。在本文中，我们提出了一种架构，该架构增加了内置上下文的虚拟数量，并通过在多任务环境中在处理器和内存之间分层分配和交换任务上下文来实现无缝任务切换。同时，我们的目标是通过基于任务优先级的分层任务分配和利用多上下文架构的中断请求快速响应机制来支持实时应用。此外，我们提出了两种可重构缓存应用，基于优先级的分区缓存和FIFO缓存，以及它们的实现方法。我们对通用RISC处理器架构进行了扩展，并正在开发一种新的RISC内核，该内核可用于实现无缝任务切换、快速响应中断请求和可重构缓存，以支持多任务环境下的实时处理。本文描述了RISC内核的设计。
A multithreaded processor architecture enables fast context switching for tolerating memory access latency and bridging synchronization gap, and thus enables efficient utilization of execution pipelines. However, it cannot prevent all pipeline stalls; stalls will still occur when all processor built-in threads are in a wait state or there are not enough threads in a task to fill up all available context slots, since the mechanism for switching active threads is effective only for processor built-in contexts. In this paper, we propose an architecture that increases the virtual number of built-in contexts and enables seamless task switching by allocating and swapping task contexts hierarchically between processor and memory in a multitasking environment. At the same time, we aim at supporting real-time applications through hierarchical task allocation based on task priority and fast response mechanisms for interrupt requests exploiting the multiple-context architecture. Moreover, we propose two reconfigurable cache applications, a priority-based partitioning cache and a FIFO buffer, and their implementation methods. We have extended the general-purpose RISC processor architecture and are developing a new RISC core which can be used to implement the seamless task switching, fast response to interrupt requests, and the reconfigurable caches, for supporting real-time processing in a multi-tasking environment. we describe the design of the RISC core in this paper.