Novel First-Level Interconnect Techniques for Flip Chip on MEMS Devices.

Novel First-Level Interconnect Techniques for Flip Chip on MEMS Devices.
复制标题

DOI:
10.1109/jmems.2011.2171326
复制
发表时间:
2011-11-03
期刊:
Journal of microelectromechanical systems : a joint IEEE and ASME publication on microstructures, microactuators, microsensors, and microsystems
影响因子:
--
通讯作者:
Muthuswamy J
Muthuswamy J
中科院分区:
其他
文献类型:
--
作者:
Sutanto J;Anand S;Patel C;Muthuswamy J

文献摘要

被引文献

相似文献

倒装芯片封装对于微机电系统(MEMS)器件是期望的,因为它减小了总体封装尺寸并且允许通过3-D堆叠按比例增加MEMS芯片的数量。在这份报告中,我们展示了三种新的技术,以创建一级互连(FLI)的MEMS:1)浸和附着技术的银环氧树脂; 2)分配技术的焊膏; 3)分配,拉,并附着技术(DPAT)的焊膏。上述技术不需要额外的微加工步骤,不会在MEMS有源结构上产生可见的表面污染,并产生高纵横比互连。所开发的FLIs在由SUMMiTVTM工艺微制造的MEMS可移动微电极上成功地进行了测试,由于释气没有产生明显的有害影响。在100 μm × 100 μm的Al沉积焊盘上成功地进行了凸点工艺,Ag的平均凸点高度为101.3 μm,焊料(63 Sn,37 Pb)的平均凸点高度为184.8 μm。用于焊膏的DPAT产生了纵横比为1.8或更大的凸块。银和焊料凸点的平均剪切强度分别为78 MPa和689 kPa。在794 A/cm 2下对Ag凸块进行的电气测试证明了可靠的电气互连,电阻可忽略不计。这些可扩展的FLI技术对于MEMS倒装芯片封装和3-D堆叠具有潜在的用途。
Flip-chip packaging is desirable for microelectro-mechanical systems (MEMS) devices because it reduces the overall package size and allows scaling up the number of MEMS chips through 3-D stacks. In this report, we demonstrate three novel techniques to create first-level interconnect (FLI) on MEMS: 1) Dip and attach technology for Ag epoxy; 2) Dispense technology for solder paste; 3) Dispense, pull, and attach technology (DPAT) for solder paste. The above techniques required no additional microfabrication steps, produced no visible surface contamination on the MEMS active structures, and generated high-aspect-ratio interconnects. The developed FLIs were successfully tested on MEMS moveable microelectrodes microfabricated by SUMMiTVTM process producing no apparent detrimental effect due to outgassing. The bumping processes were successfully applied on Al-deposited bond pads of 100 μm × 100 μm with an average bump height of 101.3 μm for Ag and 184.8 μm for solder (63Sn, 37Pb). DPAT for solder paste produced bumps with the aspect ratio of 1.8 or more. The average shear strengths of Ag and solder bumps were 78 MPa and 689 kPa, respectively. The electrical test on Ag bumps at 794 A/cm2 demonstrated reliable electrical interconnects with negligible resistance. These scalable FLI technologies are potentially useful for MEMS flip-chip packaging and 3-D stacking.