Proximity coherence for chip multiprocessors
Proximity coherence for chip multiprocessors
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DOI：
10.1145/1854273.1854293
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发表时间：
2010-09
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通讯作者：
Nick Barrow-Williams
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作者：
Nick Barrow-Williams
众核架构提供了一种有效的方式来利用现代制造工艺中越来越多的晶体管。虽然它们类似于多节点系统，但它们表现出不同的通信延迟和存储特性，提供了以前不可行的新设计机会。传统的缓存一致性协议虽然经常用于众核设计，但却是在多节点系统的背景下开发的。因此，它们很少利用众核架构提供的新可能性。我们提出了接近一致性，一个计划，在该计划中，L1负载未命中乐观地转发到附近的缓存通过新的专用链接，而不是总是间接通过一个目录结构。这样的优化是可能的本地缓存访问的成本与片上网络资源的使用。使用嵌入在L1缓存中的轻量级图形结构来维护内聚性。我们比较我们的邻近一致性协议，现有的基于目录的MESI协议使用全系统模拟的32个核心系统。对于一系列并行基准测试，我们的扩展将L1缓存加载未命中的延迟降低了32%，同时将全局片上互连上传输的字节数减少了19%。采用Proximity Coherence可将执行时间缩短多达13%，将缓存层次结构能耗降低多达30%，并为芯片多处理器中的一致性挑战提供更高效的解决方案。
Many-core architectures provide an efficient way of harnessing the increasing numbers of transistors available in modern fabrication processes. While they are similar to multi-node systems, they exhibit different communication latency and storage characteristics, providing new design opportunities that were previously not feasible. Traditional cache coherence protocols, although often used in many-core designs, have been developed in the context of multi-node systems. As such, they seldom take advantage of the new possibilities that many-core architectures offer. We propose Proximity Coherence, a scheme in which L1 load misses are optimistically forwarded to nearby caches via new dedicated links rather than always being indirected via a directory structure. Such an optimization is made possible by the comparable cost of local cache accesses with the use of on-chip network resources. Coherency is maintained using lightweight graph structures embedded in the L1 caches. We compare our Proximity Coherence protocol to an existing directory-based MESI protocol using full-system simulations of a 32 core system. Our extension lowers the latency of L1 cache load misses by up to 32% while reducing the bytes transferred on the global on-chip interconnect by up to 19% for a range of parallel benchmarks. Employing Proximity Coherence provides execution time improvements of up to 13%, reduces cache hierarchy energy consumption by up to 30% and delivers a more efficient solution to the challenge of coherence in chip multiprocessors.