Two-dimensional common-centroid stack generation algorithms for analog VLSI
Two-dimensional common-centroid stack generation algorithms for analog VLSI
复制标题
模拟 VLSI 的二维共质心堆栈生成算法
DOI：
10.1109/icasic.2003.1277506
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发表时间：
2003
期刊：
影响因子：
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通讯作者：
Jun Gu Jun Gu
中科院分区：
文献类型：
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作者：
Rui Liu Rui Liu;Sheqin Dong Sheqin Dong;Xianlong Hong Xianlong Hong;Di Long Di Long;Jun Gu Jun Gu
在模拟超大规模集成电路设计中，二维共质心叠层（其中器件是二维对称的并且具有共质心）对于失配最小化和寄生控制至关重要。然而，由于布局的几个限制，很难构建。本文描述了模拟VLSI二维共质心堆栈的生成算法。通过对对称欧拉图和对称欧拉迹的研究，得到了一些理论结果。在此基础上，开发了虚拟晶体管插入、对称欧拉轨迹构建和二维共形心堆栈构建的O（n）算法。所生成的堆栈是二维对称和共质心的。对于一组器件，可以生成具有不同比率的多个堆叠，并且可以在放置期间根据性能和面积考虑来选择它们。实验结果表明了算法的有效性。
In analog VLSI design, two-dimensional common-centroid stacks, in which devices are two-dimensional symmetry and have a common-centroid, are critical for mismatch minimization and parasitic control. However it is difficult to construct due to several constrains of layout. In this paper, algorithms for generating analog VLSI two-dimensional common-centroid stack are described. We get several theory results by studying symmetric Eulerian graph and symmetric Eulerian trail. Based on those, an O(n) algorithm for dummy transistor insertion, symmetric Eulerian trail construction and two-dimensional common-centroid stack construction are developed. The generated stacks are two-dimensional symmetric and common-centroid. Several stacks with different ratio are generated for one group of devices and they could be chosen during placement according to the performance and area consideration. Experimental results show effectiveness of our algorithms.