Asynchronous circuit design on reconfigurable devices
Asynchronous circuit design on reconfigurable devices
复制标题
可重构器件的异步电路设计
DOI：
10.1145/1150343.1150355
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发表时间：
2006
期刊：
影响因子：
--
通讯作者：
A. Reis
中科院分区：
文献类型：
--
作者：
R. U. R. Mocho;G. H. Sartori;R. Ribas;A. Reis
本文介绍了基于同步fpga和cpld的异步电路设计。通过实现双轨全加法器和纹波进位加法器以及基于自定时环的应用，研究了不同的设计风格。通过在标准可编程逻辑器件上对电路进行原型设计，并使用供应商提供的开发工具进行对比分析。虽然异步电路的可行性已经在这种设备上得到了证明，但实验结果清楚地表明这种数字系统实现的低效率。这主要是由于可编程器件的体系结构特点和开发环境所实现的逻辑综合。本研究对致力于异步设计的新型FPGA架构提出了意见和建议。
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full adders and ripple carry adders, as well as self-timed ring based applications. The comparison analysis has been carried out by prototyping the circuits on standard programmable logic devices, and using the development tools provided by vendors. Although the feasibility of asynchronous circuits has been demonstrated in such devices, the experimental results clearly show the inefficiency of such a kind of digital system implementation. This is mainly due to the architecture characteristics of the programmable devices and the logic synthesis realized by the development environments. Remarks and suggestions are derived from this study for a new FPGA architecture devoted to asynchronous design.