RF CMOS fully-integrated heterodyne front-end receivers design technique for 5 GHz applications
RF CMOS fully-integrated heterodyne front-end receivers design technique for 5 GHz applications
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DOI:
10.1109/iscas.2004.1328356
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发表时间:
2004-05
期刊:
影响因子:
--
通讯作者:
R. A. Baki;M. El-Gamal
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文献类型:
--
作者:
R. A. Baki;M. El-Gamal
This paper presents an architecture that allows the implementation of fully integrated heterodyne 5GHz RF receivers. The front-end circuitry consists of a low noise amplifier, a critical cascade of two notch filters, an active mixer, and a voltage controlled oscillator. The notch filters, which use on chip inductor Q-factor enhancement techniques, are designed to provide a wide bandwidth of image rejection (IR), eliminating the need for accurate IR tuning circuitry. More than 40dB of image rejection can be obtained in a standard 0.18/spl mu/m CMOS technology, for a 400MHz bandwidth centered at 7.2GHz, without having to resort to the overhead and the complexity of automatic tuning circuits. Design issues of homodyne and heterodyne 5GHz front-end receivers are received and discussed.