Sub-THz interconnect for planar chip-to-chip communications
Sub-THz interconnect for planar chip-to-chip communications
复制标题
用于平面芯片间通信的次太赫兹互连
DOI：
10.1109/sirf.2018.8304228
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发表时间：
2018
期刊：
影响因子：
--
通讯作者：
Q. Gu
中科院分区：
文献类型：
--
作者：
Bo Yu;Y. Ye;Xuan Ding;C. Neher;X. Liu;Zhiwei Xu;Q. Gu
本文提出了基于微带线和基于介质波导的亚太赫兹互连的高能量效率和高带宽密度芯片到芯片通信。信道损耗为0.06dB/mm的微带线互连和信道损耗为0.04dB/mm的介质波导互连的数据速率分别达到12.2Gb/s和12.1Gb/s。实现的最高能量效率和带宽密度高达0.32 pJ/B和100 Gb/s/mm 2。
This paper presents both microstrip line based and dielectric waveguide based sub-THz interconnect for high energy efficiency and high bandwidth density chip-to-chip communications. The data rates of microstrip line based interconnect with 0.06-dB/mm channel loss and dielectric waveguide based interconnect with 0.04-dB/mm channel loss are up to 12.2 Gb/s and 12.1 Gb/s, respectively. The highest energy efficiency and bandwidth density achieved are up to 0.32 pJ/b and 100 Gb/s/mm2.