FASED: FPGA-Accelerated Simulation and Evaluation of DRAM
FASED: FPGA-Accelerated Simulation and Evaluation of DRAM
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FASED：FPGA 加速 DRAM 仿真和评估
DOI：
10.1145/3289602.3293894
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
K. Asanović
中科院分区：
文献类型：
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作者：
David Biancolin;S. Karandikar;Donggyu Kim;Jack Koenig;Andrew Waterman;J. Bachrach;K. Asanović
最近在ASIC的现场可编程门阵列加速仿真方面的工作表明，大部分仿真器可以从ASIC RTL自动生成。可惜，这些工作依赖于外部高速缓存层次结构和DRAM的简单模型，因为将这些组件的ASIC RTL映射到FPGA结构过于复杂和资源密集型。为了提高模拟模型的精度，我们提出了一个可组合的、高保真的、由现场可编程门阵列托管的末级缓存和DRAM模型的参数化生成器FASE D。FASED实例具有很高的性能，但它们独立于主机-FPGA存储系统的行为来维护时间准确性。对于给定的调度策略，单个FASED实例可以对可实现的单通道DDR3内存组织的几乎整个空间进行建模，而无需重新综合模拟器RTL。我们通过将FASE D集成到一个流程中进行演示，该流程可将多核RISC-V处理器的RTL自动转换为全系统模拟器，在云托管的现场可编程门阵列上以高达150目标MHz的速度执行。
Recent work in FPGA-accelerated simulation of ASICs has shown that much of a simulator can be automatically generated from ASIC RTL. Alas, these works rely on simple models of the outer cache hierarchy and DRAM, as mapping ASIC RTL for these components into an FPGA fabric is too complex and resource intensive. To improve FPGA simulation model accuracy, we present FASED, a parameterized generator of composable, high-fidelity, FPGA-hosted last-level-cache and DRAM models. FASED instances are highly performant, yet they maintain timing faithfulness independently of the behavior of the host-FPGA memory system. For a given scheduling policy, a single FASED instance can model nearly the entire space of realizable single-channel DDR3 memory organizations, without resynthesizing the simulator RTL. We demonstrate FASED by integrating it into a flow that automatically transforms RTL for multicore RISC-V processors into full-system simulators that execute at up to 150 target MHz on cloud-hosted FPGAs.