Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology
Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology
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DOI：
10.1109/tdmr.2007.910130
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发表时间：
2007-12
影响因子：
2
通讯作者：
Wenping Wang;V. Reddy;A. Krishnan;R. Vattikonda;S. Krishnan;Yu Cao
中科院分区：
文献类型：
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作者：
Wenping Wang;V. Reddy;A. Krishnan;R. Vattikonda;S. Krishnan;Yu Cao
负偏置温度不稳定性（NBTI）和通道热载流子（CHC）是纳米级晶体管可靠性的主要问题。分析CHC的实际建模方法是基于衬底电流Isub，随着技术的扩展，各种泄漏元件主导Isub，这变得越来越成问题。在本文中，我们提出了一种统一的方法，可以直接预测NBTI和CHC效应在不同工艺和设计条件下晶体管关键参数的变化。利用一般的反应扩散模型和表面电位的概念，该方法连续捕获了亚阈值和强反转区域的性能退化。模型全面验证与工业65纳米技术。通过对环形振荡器的测量数据和放大器的仿真进行基准测试，我们证明了所提出的方法可以很好地预测电路性能的退化。对于65nm工艺，NBTI是主要的可靠性问题，而CHC对电路性能的影响相对较小。
Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current Isub, which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this paper, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65-nm technology. By benchmarking the prediction of circuit performance degradation with the measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method very well predicts the degradation. For 65-nm technology, NBTI is the dominant reliability concern, and the impact of CHC on circuit performance is relatively small.