A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication
A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication
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DOI：
10.1109/jssc.2009.2014203
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发表时间：
2009-03
影响因子：
5.4
通讯作者：
M. Pozzoni;S. Erba;P. Viola;M. Pisati;Emanuele Depaoli;D. Sanzogni;R. Brama;D. Baldi;M. Repossi;F. Svelto
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文献类型：
--
作者：
M. Pozzoni;S. Erba;P. Viola;M. Pisati;Emanuele Depaoli;D. Sanzogni;R. Brama;D. Baldi;M. Repossi;F. Svelto
本文介绍了采用 65 nm CMOS 的 1.5 至 10 Gb/s SATA/SAS/FC 接收器。行业标准设定的多重约束要求接收器架构能够同时解决通道损耗损伤、高频差跟踪和低串行到并行延迟的问题。自适应 3 抽头 DFE 数据恢复基于直接反馈拓扑，可提供连续均衡信号，确保稳健的时钟数据自对准。基于锁存器的 DFE 拓扑结构已被开发出来，以克服经典的 DFE 反馈环路延迟问题。数字早晚时钟恢复已被证明可用于 plusmn5000 ppm SSC 跟踪。广泛的数字功能允许自校准和内眼分析。该器件采用 65 nm 技术实现，支持 6 Gb/s 以上的 36" FR4（带 SSC）和 8.5 Gb/s 的 28" FR4，同时保持 0.4 UI 的额外正弦抖动容限，1V 功耗为 140 mW。
This paper presents a 1.5 to 10 Gb/s SATA/SAS/FC receiver in 65 nm CMOS. The multiple constraints set by industry standards ask for a receiver architecture capable of simultaneously addressing channel loss impairments, high frequency-difference tracking and low serial to parallel latency. An adaptive 3-tap DFE data recovery is based on a direct-feedback topology to provide a continuous equalized signal assuring a robust clock-data self alignment. A latch-based DFE topology has been developed to overcome the classical DFE feedback loop-delay issue. A digital early-late clock recovery has been proven for plusmn5000 ppm SSC tracking. Extensive digital features allow self-calibration and internal eye analysis. The device, realized in a 65 nm technology, supports more than 36" FR4 at 6 Gb/s with SSC and 28" at 8.5 Gb/s while keeping 0.4 UI of additional sinusoidal jitter tolerance, consuming 140 mW from 1V.