Experimental characterization of the bipolar effect on P-hit single-event transients in 65 nm twin-well and triple-well CMOS technologies

Experimental characterization of the bipolar effect on P-hit single-event transients in 65 nm twin-well and triple-well CMOS technologies
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DOI:
10.1007/s11431-015-5999-5
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发表时间:
2016-03
期刊:
Science China Technological Sciences
影响因子:
--
通讯作者:
Jianjun Chen;Bin Liang;Yaqing Chi
Jianjun Chen;Bin Liang;Yaqing Chi
中科院分区:
其他
文献类型:
--
作者:
Jianjun Chen;Bin Liang;Yaqing Chi

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单粒子电荷收集由漂移、扩散和双极效应控制。先前的工作已经证实,双极效应在 90 nm 及以上技术的 p 型金属氧化物半导体场效应晶体管 (PMOS) 中非常显着。然而,双极效应对 P-hit 单粒子瞬变的影响在 65 nm 技术中尚未完全表征。在本文中,通过重离子实验在 65 nm 双阱和三阱互补金属氧化物半导体 (CMOS) 技术中表征双极效应对 P 击中单粒子瞬态的影响。探索了两个具有巧妙布局结构的逆变器链来进行表征。还使用Ge(线性能量转移(LET)= 37.4 MeV cm2/mg)和Ti(LET = 22.2 MeV cm2/mg)粒子。实验结果表明,在Ge(Ti)曝光下,当双极效应得到有效缓解时,三阱CMOS技术的平均脉冲减少量为49 ps(45 ps),双阱CMOS技术的平均脉冲减少量为42 ps(32 ps)。该表征将为抗辐射集成电路设计提供重要参考。
Single-event charge collection is controlled by drift, diffusion and the bipolar effect. Previous work has established that the bipolar effect is significant in the p-type metal-oxide-semiconductor field-effect transistor (PMOS) in 90 nm technology and above. However, the consequences of the bipolar effect on P-hit single-event transients have still not completely been characterized in 65 nm technology. In this paper, characterization of the consequences of the bipolar effect on P-hit single-event transients is performed by heavy ion experiments in both 65 nm twin-well and triple-well complementary metal-oxide-semiconductor (CMOS) technologies. Two inverter chains with clever layout structures are explored for the characterization. Ge (linear energy transfer (LET) = 37.4 MeV cm2/mg) and Ti (LET = 22.2 MeV cm2/mg) particles are also employed. The experimental results show that with Ge (Ti) exposure, the average pulse reduction is 49 ps (45 ps) in triple-well CMOS technology and 42 ps (32 ps) in twin-well CMOS technology when the bipolar effect is efficiently mitigated. This characterization will provide an important reference for radiation hardening integrated circuit design.