Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs
Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs
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DOI：
10.1109/vlsid.2018.36
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发表时间：
2018-03
期刊：
影响因子：
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通讯作者：
Anju P. Johnson;Junxiu Liu;Alan G. Millard;Shvan Karim;A. Tyrrell;J. Harkin;J. Timmis;L. McDaid;D. Halliday
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文献类型：
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作者：
Anju P. Johnson;Junxiu Liu;Alan G. Millard;Shvan Karim;A. Tyrrell;J. Harkin;J. Timmis;L. McDaid;D. Halliday
本文提出了一种基于现场可编程门阵列（FPGA）器件的神经形态系统，该系统使用一种结合了峰值时序相关可塑性（STDP）和Bienenstock， Cooper, and Munro （BCM）学习规则的学习方法来建立容错性。该规则通过将与STDP相关的可塑性窗口作为突触后神经活动的函数在垂直轴上上下移动来调节突触可塑性水平。特别是当神经元处于非活动状态时，无论是在正常学习阶段的早期，还是在故障发生时，窗口都向垂直轴上移动（打开），导致突触后神经元的放电速率增加。随着学习的进展，可塑性窗口沿着垂直轴向下移动，直到所需的突触后神经元放电速率建立。实验结果表明了该方法在建立容错性方面的有效性。系统至少有一个无故障的突触就可以维持网络性能。最后，我们讨论了利用所提出的体系结构的机器人应用。
The paper presents a neuromorphic system implemented on a Field Programmable Gate Array (FPGA) device establishing fault tolerance using a learning method, which is a combination of the Spike-Timing-Dependent Plasticity (STDP) and Bienenstock, Cooper, and Munro (BCM) learning rules. The rule modulates the synaptic plasticity level by shifting the plasticity window, associated with STDP, up/down the vertical axis as a function of postsynaptic neural activity. Specifically when neurons are inactive, either early on in the normal learning phase or when a fault occurs, the window is shifted up the vertical axis (open), leading to an increase in firing rate of the postsynaptic neuron. As learning progresses, the plasticity window moves down the vertical axis until the desired postsynaptic neuron firing rate is established. Experimental results are presented to show the effectiveness of the proposed approach in establishing fault tolerance. The system can maintain the network performance with at least one nonfaulty synapse. Finally, we discuss a robotic application utilizing the proposed architecture.