Tunnel Field-Effect Transistors: Prospects and Challenges
Tunnel Field-Effect Transistors: Prospects and Challenges
复制标题
DOI：
10.1109/jeds.2015.2390591
复制
发表时间：
2015-05-01
影响因子：
2.3
通讯作者：
Young, Ian A.
中科院分区：
文献类型：
--
作者：
Avci, Uygar E.;Morris, Daniel H.;Young, Ian A.
隧道场效应晶体管（TFET）被认为是未来的晶体管选择，因为它的陡斜率前景和由此产生的低电源电压（V-DD）下工作的优势。在本文中，使用与实验TFET器件一致的原子量子模型，我们正在审查L-G = 13 nm节点的TFET前景及其实施的主要挑战和好处。对于GaSb/InAs TFET，在与CMOS的等性能下显示出显著的功率节省，但仅针对使用低于常规V-DD的性能目标。此外，P-TFET电流驱动在N-TFET的1倍至0.5倍之间，这取决于I-OFF和V-DD的选择。在产品中实现TFET存在许多挑战，例如需要具有非常薄的主体尺寸的高质量III-V材料和氧化物，以及由于其源极/漏极不对称性而导致的TFET的布局密度和可靠性问题。然而，高度并行化的产品，如图形核心，显示出以一些芯片面积为代价的更长电池寿命的前景。
The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage (V-DD). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at L-G = 13 nm node together with the main challenges and benefits of its implementation. Significant power savings at iso-performance to CMOS are shown for GaSb/InAs TFET, but only for performance targets which use lower than conventional V-DD. Also, P-TFET current-drive is between 1x to 0.5x of N-TFET, depending on choice of I-OFF and V-DD. There are many challenges to realizing TFETs in products, such as the requirement of high quality III-V materials and oxides with very thin body dimensions, and the TFET's layout density and reliability issues due to its source/drain asymmetry. Yet, extremely parallelizable products, such as graphics cores, show the prospect of longer battery life at a cost of some chip area.